- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄190254 > PSD833F2-15M 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52 PDF資料下載
參數(shù)資料
| 型號： | PSD833F2-15M |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1M X 1 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52 |
| 封裝： | PLASTIC, QFP-52 |
| 文件頁數(shù)： | 76/122頁 |
| 文件大?。?/td> | 489K |
| 代理商： | PSD833F2-15M |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁當(dāng)前第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁
Preliminary Information
PSD8XXF Family
53
The
PSD8XXF
Functional
Blocks
(cont.)
Control
Direction
VM
Defined In
Register
JTAG
Mode
PSDabel
PSDconfiguration
Setting
Enable
Declare
1 = output,
MCU I/O
pins only
NA*
0
0 = input
NA
(Note 1)
PLD I/O
Logic
NA
(Note 1)
NA
equations
Data Port
NA
Specify bus type
NA
(Port A)
Address Out
Declare
NA
1
1 (Note 1)
NA
(Port A,B)
pins only
Address In
Logic equation
(Port A,B,C,D)
for Input
NA
Micro
Cells
Peripheral I/O
Logic equations
NA
PIO bit = 1
NA
(Port A)
(PSEL0 & 1)
JTAG ISP
JTAGSEL
JTAG Configuration
NA
JTAG_
(Note 2)
Enable
Table 21. Port Operating Mode Settings
*NA = Not Applicable
NOTE: 1. The direction of the Port A,B,C, and D pins are controlled by the Direction Register ORed with the
individual output enable product term (.oe) from the CPLD AND array.
2. Any of these three methods will enable JTAG pins on Port C.
9.4.2.1 MCU I/O Mode
In the MCU I/O Mode, the microcontroller uses the PSD8XXF ports to expand its own
I/O ports. By setting up the CSIOP space, the ports on the PSD8XXF are mapped into the
microcontroller address space. The addresses of the ports are listed in Table 7.
A port pin can be put into MCU I/O mode by writing a ‘0’ to the corresponding bit in the
Control Register. The MCU I/O direction may be changed by writing to the corresponding
bit in the Direction Register, or by the output enable product term. See the subsection on
the Direction Register in the “Port Registers” section. When the pin is configured as an
output, the content of the Data Out Register drives the pin. When configured as an input,
the microcontroller can read the port input through the Data In buffer. See Figure 22.
Ports C and D do not have Control Registers, and are in MCU I/O mode by default. They
can be used for PLD I/O if equation are written for them in PSDabel.
9.4.2.2 PLD I/O Mode
The PLD I/O Mode uses a port as an input to the CPLD’s Input Micro
Cells, and/or as an
output from the CPLD’s Output Micro
Cells. The output can be tri-stated with a control
signal. This output enable control signal can be defined by a product term from the PLD, or
by setting the corresponding bit in the Direction Register to ‘0’. The corresponding bit in the
Direction Register must not be set to ‘1’ if the pin is defined as a PLD input pin in PSDabel.
The PLD I/O Mode is specified in PSDabel by declaring the port pins, and then writing an
equation assigning the PLD I/O to a port.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PSD835G2V-B-90MI | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| PSD835G2V-B-90U | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| PSD835G2V-B-90UI | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| PSD835G2V-C-12B81I | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| PSD835G2V-C-12M | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD833F2-90J | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD833F2-90JI | 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD833F2-90M | 功能描述:SPLD - 簡單可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Texas Instruments 邏輯系列:TICPAL22V10Z 大電池數(shù)量:10 最大工作頻率:66 MHz 延遲時間:25 ns 工作電源電壓:4.75 V to 5.25 V 電源電流:100 uA 最大工作溫度:+ 75 C 最小工作溫度:0 C 安裝風(fēng)格:Through Hole 封裝 / 箱體:DIP-24 |
| PSD833F2-90MI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 5.0V 1M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD834F2-15M | 制造商:STMicroelectronics 功能描述:Flash In-System Programmable Peripherals 52-Pin PQFP |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。