參數(shù)資料
型號(hào)： PSD4235G2-90UT
廠商： STMICROELECTRONICS
元件分類(lèi)： 微控制器/微處理器
英文描述： 256K X 16 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80
封裝： PLASTIC, TQFP-80
文件頁(yè)數(shù)： 74/100頁(yè)
文件大?。?/td> 933K
代理商： PSD4235G2-90UT
75/100
PSD4235G2
Figure 34. Reset (RESET) Timing
PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE
The JTAG Serial Interface on the PSD can be en-
abled on Port E (see Table 52). All memory blocks
(primary Flash memory and secondary Flash
memory), PLD logic, and PSD Configuration bits
may be programmed through the JTAG-ISC Serial
Interface. A blank device can be mounted on a
printed circuit board and programmed using JTAG
In-System Programming (ISP).
The standard JTAG signals (IEEE 1149.1) are
TMS, TCK, TDI, and TDO. Two additional signals,
TSTAT and TERR, are optional JTAG extensions
used to speed up Program and Erase cycles.
By default, on a blank PSD (as shipped from the
factory, or after erasure), four pins on Port E are
enabled for the basic JTAG signals TMS, TCK,
TDI, and TDO.
See Application Note AN1153 for more details on
JTAG In-System Programming (ISP).
Standard JTAG Signals
The standard JTAG signals (TMS, TCK, TDI, and
TDO) can be enabled by any of three different con-
ditions that are logically ORed. When enabled,
TDI, TDO, TCK, and TMS are inputs, waiting for a
serial command from an external JTAG controller
device (such as FlashLINK or Automated Test
Equipment). When the enabling command is re-
ceived from the external JTAG controller device,
TDO becomes an output and the JTAG channel is
fully functional inside the PSD. The same com-
mand that enables the JTAG channel may option-
ally enable the two additional JTAG pins, TSTAT
and TERR.
The following symbolic logic equation specifies the
conditions enabling the four basic JTAG pins
(TMS, TCK, TDI, and TDO) on their respective
Port E pins. For purposes of discussion, the logic
label JTAG_ON is used. When JTAG_ON is true,
the four pins are enabled for JTAG. When
JTAG_ON is false, the four pins can be used for
general PSD I/O.
JTAG_ON = PSDsoft Express_enabled +
/* An NVM configuration bit inside the
PSD
is
set
by
the
designer
in
the
PSDsoft Express Configuration utility.
This dedicates the pins for JTAG at all
times (compliant with IEEE 1149.1 */
Microcontroller_enabled +
/* The microcontroller can set a bit at
run-time
by
writing
to
the
PSD
register,
JTAG
Enable.
This
register
is
located
at
address
CSIOP
+
offset
C7h.
Setting
the
JTAG_ENABLE
bit
in
this register will enable the pins for
JTAG use. This bit is cleared by a PSD
reset
or
the
microcontroller.
See
Table 21 for bit definition. */
PSD_product_term_enabled;
/* A dedicated product term (PT) inside
the PSD can be used to enable the JTAG
pins.
This
PT
has
the
reserved
name
JTAGSEL.
Once
defined
as
a
node
in
PSDabel,
the
designer
can
write
an
equation
for
JTAGSEL.
This
method
is
used
when
the
Port
E
JTAG
pins
are
multiplexed with other I/O signals. It
is
recommended
to
tie
logically
the
node JTAGSEL to the JEN\ signal on the
Flashlink cable when multiplexing JTAG
signals. See Application Note 1153 for
details. */
tNLNH-PO
tOPR
AI02866b
RESET
tNLNH
tNLNH-A
tOPR
VCC
V
CC(min)
Power-On Reset
Warm Reset
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