參數(shù)資料
型號： PSD4235G2-90UT
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 256K X 16 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80
封裝： PLASTIC, TQFP-80
文件頁數(shù)： 61/100頁
文件大?。?/td> 933K
代理商： PSD4235G2-90UT
63/100
PSD4235G2
JTAG In-System Programming (ISP)
Port E is JTAG compliant, and can be used for In-
System Programming (ISP). You can multiplex
JTAG operations with other functions on Port E
because In-System Programming (ISP) is not per-
formed during normal system operation. For more
information on the JTAG Port, see the section en-
MCU Reset Mode
Ports F and G can be configured to operate in
MCU Reset mode. This mode is available when
PSD is configured for the Motorola 16-bit 683xx
and HC16 family and is active only during reset.
At the rising edge of the Reset input, the MCU
reads the logic level on the data bus (D15-D0)
pins. The MCU then configures some of its I/O pin
functions according to the logic level input on the
data bus lines. Two dedicated buffers are usually
enabled during reset to drive the data bus lines to
the desired logic level.
The PSD can replace the two buffers by configur-
ing Ports F and G to operate in MCU Reset mode.
In this mode, the PSD will drive the pre-defined
logic level or data pattern on to the MCU data bus
when Reset is active and there is no ongoing bus
cycle. After reset, Ports F and G return to the nor-
mal Data Port mode.
The MCU Reset mode is enabled and configured
in PSDsoft Express. The user defines the logic lev-
el (data pattern) that will be drive out from Ports F
and G during reset.
Port Configuration Registers (PCR)
Each Port has a set of Port Configuration Regis-
ters (PCR) used for configuration. The contents of
the registers can be accessed by the MCU through
normal READ/WRITE bus cycles at the addresses
given in Table 6. The addresses in Table 6 are the
offsets in hexadecimal from the base of the CSIOP
register.
The pins of a port are individually configurable and
each bit in the register controls its respective pin.
For example, Bit 0 in a register refers to Bit 0 of its
port. The three Port Configuration Registers
(PCR), shown in Table 42, are used for setting the
Port configurations. The default Power-up state for
each register in Table 42 is 00h.
Control Register
Any bit reset to ’0’ in the Control Register sets the
corresponding port pin to MCU I/O mode, and a ’1’
sets it to Address Out mode. The default mode is
MCU I/O. Only Ports E, F and G have an associat-
ed Control Register.
Table 42. Port Configuration Registers (PCR)
Note: 1. See Table 46 for Drive Register Bit definition.
Register Name
Port
MCU Access
Control
E, F, G
WRITE/READ
Direction
A, B, C, D, E, F, G WRITE/READ
Drive Select1
A, B, C, D, E, F, G WRITE/READ
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