參數(shù)資料
型號(hào)： PSD4235G2-90UT
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 256K X 16 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80
封裝： PLASTIC, TQFP-80
文件頁(yè)數(shù)： 29/100頁(yè)
文件大小： 933K
代理商： PSD4235G2-90UT
PSD4235G2
34/100
SPECIFIC FEATURES
Flash Memory Sector Protect
Each sector of Primary or Secondary Flash mem-
ory can be separately protected against Program
and Erase cycles. Sector Protection provides ad-
ditional data security because it disables all Pro-
gram or Erase cycles. This mode can be activated
(or deactivated) through the JTAG-ISP Port or a
Device Programmer.
Sector protection can be selected for each sector
using the PSDsoft Express program. This auto-
matically protects selected sectors when the de-
vice is programmed through the JTAG Port or a
Device Programmer. Flash memory sectors can
be unprotected to allow updating of their contents
using the JTAG Port or a Device Programmer. The
MCU can read (but cannot change) the sector pro-
tection bits.
Any attempt to program or erase a protected Flash
memory sector is ignored by the device. The Verify
operation results in a READ of the protected data.
This allows a guarantee of the retention of the Pro-
tection status.
The sector protection status can be read by the
MCU through the Flash memory protection and
Secondary Flash memory protection registers (in
the CSIOP block) or use the Read Sector Protec-
tion instruction. See Table 19 to Table 20.
RESET
The RESET instruction consists of one WRITE cy-
cle (see Table 29). It can also be optionally pre-
ceded by the standard two WRITE decoding
cycles (writing AAh to AAAh, and 55h to 554h).
The Reset instruction must be executed after:
–
Reading the Flash Protection Status or Flash
ID
–
An Error condition has occurred (and the
device has set the Error Flag Bit (DQ5/DQ13)
to ’1’) during a Flash memory Program or
Erase cycle.
The Reset instruction immediately puts the Flash
memory back into normal READ mode. However,
if there is an error condition (with the Error Flag Bit
(DQ5/DQ13) set to ’1’) the Flash memory will re-
turn to the READ mode in 25
s after the Reset in-
struction is issued.
The Reset instruction is ignored when it is issued
during a Program or Bulk Erase cycle of the Flash
memory. The Reset instruction aborts any on-go-
ing Sector Erase cycle, and returns the Flash
memory to the normal READ mode in 25
s.
Reset (RESET) Pin
A pulse on the Reset (RESET) pin aborts any cy-
cle that is in progress, and resets the Flash mem-
ory to the READ mode. When the reset occurs
during a Program or Erase cycle, the Flash mem-
ory takes up to 25
s to return to the READ mode.
It is recommended that the Reset (RESET) pulse
(except for Power On Reset, as described on page
74) be at least 25
s so that the Flash memory is
always ready for the MCU to fetch the bootstrap in-
structions after the Reset cycle is complete.
SRAM
The SRAM is enabled when SRAM Select (RS0)
from the DPLD is High. SRAM Select (RS0) can
contain up to three product terms, allowing flexible
memory mapping.
The SRAM can be backed up using an external
battery. The external battery should be connected
to the Voltage Stand-by (VSTBY, PE6) line. If you
have an external battery connected to the PSD,
the contents of the SRAM are retained in the event
of a power loss. The contents of the SRAM are re-
tained so long as the battery voltage remains at 2V
or greater. If the supply voltage falls below the bat-
tery voltage, an internal power switch-over to the
battery occurs.
PE7 can be configured as an output that indicates
when power is being drawn from the external bat-
tery. This Battery-on Indicator (VBATON, PE7)
signal is High when the supply voltage falls below
the battery voltage and the battery on Voltage
Stand-by (VSTBY, PE6) is supplying power to the
internal SRAM.
SRAM Select (RS0), Voltage Stand-by (VSTBY,
PE6) and Battery-on Indicator (VBATON, PE7)
are all configured using PSDsoft Express.
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