參數(shù)資料
型號(hào)： PSD4235G2-90UT
廠商： STMICROELECTRONICS
元件分類(lèi)： 微控制器/微處理器
英文描述： 256K X 16 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80
封裝： PLASTIC, TQFP-80
文件頁(yè)數(shù)： 66/100頁(yè)
文件大?。?/td> 933K
代理商： PSD4235G2-90UT
PSD4235G2
68/100
Port E - Functionality and Structure
Port E can be configured to perform one or more
of the following functions (see Figure 31):
■
MCU I/O Mode
■
In-System Programming (ISP) - JTAG port
can be enabled for programming/erase of the
PSD device. (See the section entitled “Reset
information on JTAG programming.)
■
Open Drain - pins can be configured in Open
Drain Mode
■
Battery Backup features
–
PE6 can be configured for a battery input
supply, Voltage Stand-by (VSTBY).
–
PE7 can be configured as a Battery-on
Indicator (VBATON), indicating when VCC
is less than VBAT.
■
Latched Address output - Provide latched
address output.
Port F - Functionality and Structure
Port F can be configured to perform one or more
of the following functions:
■
MCU I/O Mode
■
CPLD Output - External Chip Select (ECS7-
ECS0) can be connected to Port F or Port C.
■
CPLD Input - direct input to the CPLD, no
Input Macrocells (IMC)
■
Latched Address output - Provide latched
address output as per Table 41.
■
Slew Rate - pins can be configured for fast
Slew Rate
■
Data Port - connected to D7-D0 when Port F is
configured as Data Port for a non-multiplexed
bus
■
Peripheral Mode
■
MCU Reset Mode - for 16-bit Motorola 683xx
and HC16 MCUs
Port G - Functionality and Structure
Port G can be configured to perform one or more
of the following functions:
■
MCU I/O Mode
■
Latched Address output - Provide latched
address output as per Table 41.
■
Open Drain - pins can be configured in Open
Drain Mode
■
Data Port - connected to D15-D8 when Port G
is configured as Data Port for a non-
multiplexed bus
■
MCU Reset Mode - for 16-bit Motorola 683xx
and HC16 MCUs
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