參數(shù)資料
型號(hào)： PSD4235G2-90UT
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 256K X 16 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80
封裝： PLASTIC, TQFP-80
文件頁(yè)數(shù)： 62/100頁(yè)
文件大小： 933K
代理商： PSD4235G2-90UT
PSD4235G2
64/100
Direction Register
The Direction Register controls the direction of
data flow in the I/O Ports. Any bit set to ’1’ in the
Direction Register causes the corresponding pin
to be an output, and any bit set to ’0’ causes it to
be an input. The default mode for all port pins is in-
put.
Figure 29 and Figure 31 show the Port Architec-
ture diagrams for Ports A/B/C and E/F/G, respec-
tively. The direction of data flow for Ports A, B, C
and F are controlled not only by the direction reg-
ister, but also by the output enable product term
from the PLD AND Array. If the output enable
product term is not active, the Direction Register
has sole control of a given pin’s direction.
An example of a configuration for a Port with the
three least significant bits set to output and the re-
mainder set to input is shown in Table 45. Since
Port D only contains four pins, the Direction Reg-
ister for Port D has only the four least significant
bits active.
Drive Select Register. The Drive Select Register
configures the pin driver as Open Drain or CMOS
for some port pins, and controls the slew rate for
the other port pins. An external pull-up resistor
should be used for pins configured as Open Drain.
A pin can be configured as Open Drain if its corre-
sponding bit in the Drive Select Register is set to a
'1.' The default pin drive is CMOS.
(The slew rate is a measurement of the rise and
fall times of an output. A higher slew rate means a
faster output response and may create more elec-
trical noise. A pin operates in a high slew rate
when the corresponding bit in the Drive Register is
set to '1.' The default rate is slow slew.)
Table 46 shows the Drive Register for Ports A, B,
C, D, E, F and G. It summarizes which pins can be
configured as Open Drain outputs and which pins
the slew rate can be set for.
Table 43. Port Pin Direction Control, Output
Enable P.T. Not Defined
Table 44. Port Pin Direction Control, Output
Enable P.T. Defined
Table 45. Port Direction Assignment Example
Table 46. Drive Register Pin Assignment
Note: 1. NA = Not Applicable.
Direction Register Bit
Port Pin Mode
0
Input
1
Output
Direction
Register Bit
Output Enable
P.T.
Port Pin Mode
0
Input
0
1
Output
1
0
Output
1
Output
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
1
Drive
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Port A
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Port B
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Port C
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Port D
NA1
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Port E
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Port F
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Slew
Rate
Port G
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
Open
Drain
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