參數(shù)資料
型號： PSD4235G2-90UT
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 256K X 16 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80
封裝： PLASTIC, TQFP-80
文件頁數(shù)： 50/100頁
文件大?。?/td> 933K
代理商： PSD4235G2-90UT
53/100
PSD4235G2
80C51XA
The Philips 80C51XA MCU has a 16-bit multi-
plexed bus with burst cycles. Address bits (A3-A1)
are not multiplexed, while (A19-A4) are multi-
plexed with data bits (D15-D0).
The PSD4235G2 supports the 80C51XA burst
mode. The WRH signal is connected to PD3, and
WHL is connected to CNTL0. The RD and PSEN
signals are connected to the CNTL1 and CNTL2
pins. Figure 23 shows the schematic diagram.
The 80C51XA improves bus throughput and per-
formance by issuing burst cycles to fetch codes
from memory. In burst cycles, address A19-A4 are
latched internally by the PSD, while the 80C51XA
drives the A3-A1 signals to fetch sequentially up to
16 bytes of code. The PSD access time is then
measured from address A3-A1 valid to data in val-
id. The PSD bus timing requirement in a burst cy-
cle is identical to the normal bus cycle, except the
address setup and hold time with respect to Ad-
dress Strobe (ALE/AS, PD0) is not required.
Figure 23. Interfacing the PSD with an 80C51XA-G3
VCC_BAR
D[15:0]
WRL\
RD\
PSEN\
ALE
A4D0
A5D1
A6D2
A7D3
A8D4
A9D5
A10D6
A11D7
A12D8
A13D9
A14D10
A15D11
A16D12
A17D13
A18D14
A19D15
RESET\
A3
A2
A1
WRH\
A[3:1]
A1
A2
A3
U3
CRYSTAL
PSD
ADIO0
3
ADIO1
4
ADIO2
5
ADIO3
6
ADIO4
7
ADIO5
10
ADIO6
11
ADIO7
12
ADIO9
14
ADIO10
15
ADIO11
16
ADIO12
17
ADIO13
18
ADIO14
19
ADIO15
20
PF0
31
PF1
32
PF2
33
PF3
34
PF4
35
PF5
36
PF6
37
PF7
38
PG1
22
PG2
23
PG3
24
PG4
25
PG5
26
PG6
27
PG7
28
PA5
56
PA6
57
PA7
58
CNTL0(WR)
59
CNTL1(RD)
60
CNTL2(PSEN)
40
PD0 (ALE)
79
RESET
39
ADIO8
13
PG0
21
PA3
54
PA4
55
PA2
53
PA0
51
PA1
52
PB0
61
PB1
62
PB2
63
PB3
64
PB4
65
PB5
66
PB6
67
PB7
68
PC0
41
PC1
42
PC2
43
PC3
44
PC4
45
PC5
46
PC6
47
PC7
48
PE0 (TMS)
71
PE1 (TCK/ST)
72
PE2 (TDI)
73
PE3 (TDO)
74
PE4 (TSTAT/RDY)
75
PE5 (TERR)
76
PE7 (VBATON)
78
Vcc
29
Vcc
69
Vcc
9
G
ND
50
G
ND
49
G
ND
30
G
ND
8
G
ND
70
PD2 (CSI)
1
PD1 (CLKIN)
80
PD3 (WRH)
2
PE6 (VSTBY)
77
XA-G3
A0/WRH
2
A1
3
A2
4
A3
5
A4D0
43
A5D1
42
A6D2
41
A7D3
40
A8D4
39
A9D5
38
A10D6
37
A11D7
36
A12D8
24
A13D9
25
A14D10
26
A15D11
27
A16D12
28
A17D13
29
A18D14
30
A19D15
31
PSEN
32
RD
19
WRL
18
ALE
33
RST
10
INT0
14
INT1
15
EA/WAIT
35
BUSW
17
XTAL1
21
XTAL2
20
RXD0
11
TXD0
13
RXD1
6
TXD1
7
T2EX
9
T2
8
T0
16
D[15:0]
A[3:1]
AI04952b
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