參數(shù)資料
型號: PSD4235G2-90UT
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 256K X 16 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80
封裝: PLASTIC, TQFP-80
文件頁數(shù): 52/100頁
文件大小: 933K
代理商: PSD4235G2-90UT
55/100
PSD4235G2
MMC2001
The Motorola MCORE MMC2001 MCU has a
MOD input pin that selects interal or external boot
ROM. The PSD can be configured as the external
flash boot ROM or as extension to the internal
ROM.
The MMC2001 has a 16-bit external data bus and
20 address lines with external chip select signals.
The Chip Select Control Registers allow the user
to customize the bus interface and timing to fit the
individual system requirement. A typical interface
configuaration to the PSD is shown in Figure 25.
The MMC2001’s R/W signal is conneced to the
CNTL0 pin, while EB0 and EB1 (enable byte-0 and
enable byte-1) are connected to the CNTL1 (UDS)
and CNTL2 (LDS) pins. The WEN Bit in the Chip
Select Control Register should be set to ’1’ to ter-
minate the EB0-EB1 earlier to provide the wrtie
data hold time for the PSD. The WSC and WWS
Bits in the Control Register are set to wait states
that meet the PSD access time requirement.
Another option is to configure the EB0 and EB1 as
WRL and WRH signals. In this case, the PSD con-
trol setting will be: OE, WRL, WRH where OE is
the READ signal for the MMC2001.
C16x Family
The PSD supports Infineon’s C16X family of
MCUs (C161-C167) in both the multiplexed and
non-multiplexed bus configuration. In Figure 26,
the C167CR is shown connected to the PSD in a
multiplexed bus configuration. The control signals
from the MCU are WR, RD, BHE and ALE, and are
routed to the corresponding PSD pins.
The C167 has another control signal setting (RD,
WRL, WRH, ALE) which is also supported by the
PSD.
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