參數(shù)資料
型號(hào)： PSD4235G2-90UT
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 256K X 16 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80
封裝： PLASTIC, TQFP-80
文件頁數(shù)： 60/100頁
文件大?。?/td> 933K
代理商： PSD4235G2-90UT
PSD4235G2
62/100
Address In Mode
For MCUs that have more than 16 address sig-
nals, the higher addresses can be connected to
Port A, B, C, D or F, and are routed as inputs to the
PLDs. The address input can be latched in the In-
put Macrocell (IMC) by Address Strobe (ALE/AS,
PD0). Any input that is included in the DPLD equa-
tions for the primary Flash memory, secondary
Flash memory or SRAM is considered to be an ad-
dress input.
Data Port Mode
Ports F and G can be used as a data bus port for
a MCU with a non-multiplexed address/data bus.
The Data Port is connected to the data bus of the
MCU. The general I/O functions are disabled in
Ports F and G if the ports are configured as a Data
Port. Data Port mode is automatically configured
in PSDsoft Express when a non-multiplexed bus
MCU is selected.
Peripheral I/O Mode
Peripheral I/O mode can be used to interface with
external 8-bit peripherals. In this mode, all of Port
F serves as a tri-state, bi-directional data buffer for
the MCU. Peripheral I/O mode is enabled by set-
ting Bit 7 of the VM Register to a '1.' Figure 28
shows how Port A acts as a bi-directional buffer for
the MCU data bus if Peripheral I/O mode is en-
abled. An equation for PSEL0 and/or PSEL1 must
be specified in PSDsoft Express. The buffer is tri-
stated when PSEL0 or PSEL1 is not active.
Figure 28. Peripheral I/O Mode
RD
PSEL0
PSEL1
PSEL
VM REGISTER BIT 7
WR
PA0 - PA7
D0 - D7
DATA BUS
AI02886
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