參數(shù)資料
型號： PSD4235G2-90UT
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 256K X 16 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80
封裝： PLASTIC, TQFP-80
文件頁數(shù)： 73/100頁
文件大小： 933K
代理商： PSD4235G2-90UT
PSD4235G2
74/100
POWER-ON RESET, WARM RESET AND POWER-DOWN
Power-On RESET
Upon Power-up, the PSD requires a Reset (RE-
SET) pulse of duration tNLNH-PO (minimum 1 ms)
after VCC is steady. During this period, the device
loads internal configurations, clears some of the
registers and sets the Flash memory into Operat-
ing mode. After the rising edge of Reset (RESET),
the PSD remains in the Reset mode for an addi-
tional period, tOPR (maximum 120 ns), before the
first memory access is allowed.
The PSD Flash memory is reset to the READ
mode upon Power-up. Sector Select (FS0-FS7
and CSBOOT0-CSBOOT3) must all be Low, Write
Strobe (WR/WRL, CNTL0) High, during Power On
Reset for maximum security of the data contents
and to remove the possibility of data being written
on the first edge of Write Strobe (WR/WRL,
CNTL0). Any Flash memory WRITE cycle initiation
is prevented automatically when VCC is below VL-
KO.
Warm RESET
Once the device is up and running, the device can
be reset with a pulse of a much shorter duration,
tNLNH (minimum 150 ns). The same tOPR period is
needed before the device is operational after
warm reset. Figure 34 shows the timing of the
Power-up and warm reset.
I/O Pin, Register and PLD Status at RESET
Table 51 shows the I/O pin, register and PLD sta-
tus during Power On Reset, warm reset and Pow-
er-down mode. PLD outputs are always valid
during warm reset, and they are valid in Power On
Reset once the internal PSD Configuration bits are
loaded. This loading of PSD is completed typically
long before the VCC ramps up to operating level.
Once the PLD is active, the state of the outputs are
determined by equations specified in PSDsoft Ex-
press.
Reset of Flash Memory Erase and Program
Cycles
An external Reset (RESET) also resets the inter-
nal Flash memory state machine. During a Flash
memory Program or Erase cycle, Reset (RESET)
terminates the cycle and returns the Flash memo-
ry to the READ mode within a period of tNLNH-A
(minimum 25
s).
Table 51. Status During Power-On Reset, Warm Reset and Power-down Mode
Note: 1. The SR_code and Peripheral Mode Bits in the VM Register are always cleared to ’0’ on Power-On Reset or Warm Reset.
Port Configuration
Power-On Reset
Warm Reset
Power-down Mode
MCU I/O
Input mode
Unchanged
PLD Output
Valid after internal PSD
configuration bits are
loaded
Valid
Depends on inputs to PLD
(addresses are blocked in
PD mode)
Address Out
Tri-stated
Not defined
Data Port
Tri-stated
Peripheral I/O
Tri-stated
Register
Power-On Reset
Warm Reset
Power-down Mode
PMMR0 and PMMR2
Cleared to ’0’
Unchanged
Macrocells Flip-flop status
Cleared to ’0’ by internal
Power-On Reset
Depends on .re and .pr
equations
Depends on .re and .pr
equations
VM Register1
Initialized, based on the
selection in PSDsoft
Express
Configuration menu
Initialized, based on the
selection in PSDsoft
Express
Configuration menu
Unchanged
All other registers
Cleared to ’0’
Unchanged
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