參數(shù)資料
型號(hào)： PSD4235G2-90UT
廠商： STMICROELECTRONICS
元件分類(lèi)： 微控制器/微處理器
英文描述： 256K X 16 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80
封裝： PLASTIC, TQFP-80
文件頁(yè)數(shù)： 55/100頁(yè)
文件大小： 933K
代理商： PSD4235G2-90UT
PSD4235G2
58/100
I/O PORTS
There are seven programmable I/O ports: Ports A,
B, C, D, E, F and G. Each port pin is individually
user configurable, thus allowing multiple functions
per port. The ports are configured using PSDsoft
Express or by the MCU writing to on-chip registers
in the CSIOP space.
The topics discussed in this section are:
■
General Port architecture
■
Port operating modes
■
Port Configuration Registers (PCR)
■
Port Data Registers
■
Individual Port functionality.
General Port Architecture. The general archi-
tecture of the I/O Port block is shown in Figure 27.
Individual Port architectures are shown in Figure
29 to Figure 31. In general, once the purpose for a
port pin has been defined, that pin is no longer
available for other purposes. Exceptions are not-
ed.
As shown in Figure 27, the ports contain an output
multiplexer whose select signals are driven by the
configuration bits in the Control Registers (Ports E,
F and G only) and PSDsoft Express Configuration.
Inputs to the multiplexer include the following:
■
Output data from the Data Out register
■
Latched address outputs
■
CPLD Macrocell output
■
External Chip Select from the CPLD.
The Port Data Buffer (PDB) is a tri-state buffer that
allows only one source at a time to be read. The
Port Data Buffer (PDB) is connected to the Internal
Data Bus for feedback and can be read by the
MCU. The Data Out and Macrocell outputs, Direc-
tion Register and Control Register, and port pin in-
put are all connected to the Port Data Buffer
(PDB).
The Port pin’s tri-state output driver enable is con-
trolled by a two input OR gate whose inputs come
from the CPLD AND Array enable product term
and the Direction Register. If the enable product
term of any of the Array outputs are not defined
and that port pin is not defined as a CPLD output
in the PSDabel file, the Direction Register has sole
control of the buffer that drives the port pin.
The contents of these registers can be altered by
the MCU. The Port Data Buffer (PDB) feedback
path allows the MCU to check the contents of the
registers.
Ports A, B, and C have embedded Input Macro-
cells (IMC). The Input Macrocells (IMC) can be
configured as latches, registers, or direct inputs to
the PLDs. The latches and registers are clocked
by Address Strobe (ALE/AS, PD0) or a product
term from the PLD AND Array. The outputs from
the Input Macrocells (IMC) drive the PLD input bus
and can be read by the MCU. See the section en-
Port Operating Modes
The I/O Ports have several modes of operation.
Some modes can be defined using PSDsoft Ex-
press, some by the MCU writing to the registers in
CSIOP space, and some by both. The modes that
can only be defined using PSDsoft Express must
be programmed into the device and cannot be
changed unless the device is reprogrammed. The
modes that can be changed by the MCU can be
done so dynamically at run-time. The PLD I/O,
Data Port, Address Input, Peripheral I/O and MCU
Reset modes are the only modes that must be de-
fined before programming the device. All other
modes can be changed by the MCU at run-time.
See Application Note AN1171 for more detail.
Table 39 summarizes which modes are available
on each port. Table 40 shows how and where the
different modes are configured. Each of the port
operating modes are described in the following
sections.
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