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| 型號： | PSD4235G2-90UT |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 256K X 16 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80 |
| 封裝： | PLASTIC, TQFP-80 |
| 文件頁數(shù)： | 69/100頁 |
| 文件大?。?/td> | 933K |
| 代理商： | PSD4235G2-90UT |
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PSD4235G2
70/100
POWER MANAGEMENT
The PSD device offers configurable power saving
options. These options may be used individually or
in combinations, as follows:
–
All memory blocks in a PSD (primary Flash
memory, secondary Flash memory, and
SRAM) are built with power management
technology. In addition to using special silicon
design methodology, power management
technology puts the memories into standby
mode when address/data inputs are not
changing (zero DC current). As soon as a
transition occurs on an input, the affected
memory “wakes up”, changes and latches its
outputs, then goes back to standby. The
designer does not have to do anything special
to achieve memory Stand-by mode when no
inputs are changing—it happens
automatically.
The PLD sections can also achieve Stand-by
mode when its inputs are not changing, as
described for the Power Management Mode
Registers (PMMR), later.
–
The Automatic Power Down (APD) block
allows the PSD to reduce to stand-by current
automatically. The APD Unit also blocks MCU
address/data signals from reaching the
memories and PLDs. This feature is available
on all PSD devices. The APD Unit is described
in more detail in the section entitled “APD
Built in logic monitors the Address Strobe of
the MCU for activity. If there is no activity for a
certain period (the MCU is asleep), the APD
Unit initiates Power-down mode (if enabled).
Once in Power-down mode, all address/data
signals are blocked from reaching the PSD
memories and PLDs, and the memories are
deselected internally. This allows the
memories and PLDs to remain in Stand-by
mode even if the address/data signals are
changing state externally (noise, other
devices on the MCU bus, etc.). Keep in mind
that any unblocked PLD input signals that are
changing states keeps the PLD out of Stand-
by mode, but not the memories.
–
PSD Chip Select Input (CSI, PD2) can be
used to disable the internal memories, placing
them in Stand-by mode even if inputs are
changing. This feature does not block any
internal signals or disable the PLDs. This is a
good alternative to using the APD Unit,
especially if your MCU has a chip select
output. There is a slight penalty in memory
access time when PSD Chip Select Input
(CSI, PD2) makes its initial transition from
deselected to selected.
–
The Power Management Mode Registers
(PMMR) can be written by the MCU at run-
time to manage power. All PSD devices
support “blocking bits” in these registers that
are set to block designated signals from
reaching both PLDs. Current consumption of
the PLDs is directly related to the composite
frequency of the changes on their inputs (see
Significant power savings can be achieved by
blocking signals that are not used in DPLD or
CPLD logic equations at run-time. PSDsoft
Express creates a fuse map that automatically
blocks the low address byte (A7-A0) or the
control signals (CNTL0-CNTL2, ALE and
Write Enable High-byte (WRH/DBE, PD3)) if
none of these signals are used in PLD logic
equations.
PSD devices have a Turbo Bit in PMMR0. This
bit can be set to turn the Turbo mode off (the
default is with Turbo mode turned on). While
Turbo mode is off, the PLDs can achieve
Stand-by current when no PLD inputs are
changing (zero DC current). Even when inputs
do change, significant power can be saved at
lower frequencies (AC current), compared to
when Turbo mode is on. When the Turbo
mode is on, there is a significant DC current
component, and the AC component is higher.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD4235G2V-12UI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 4M 120ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD4235G2V-90U | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 4M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD4256G6V-10UI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.3V 8M 100ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD4-36 | 制造商:Tamura Corporation of America 功能描述: |
| PSD-45 | 制造商:MEANWELL 制造商全稱:Mean Well Enterprises Co., Ltd. 功能描述:45W DC-DC Single Output Switching Power Supply |
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