參數(shù)資料
型號： PSD4235G2-90UT
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 256K X 16 FLASH, 52 I/O, PIA-GENERAL PURPOSE, PQFP80
封裝： PLASTIC, TQFP-80
文件頁數(shù)： 30/100頁
文件大?。?/td> 933K
代理商： PSD4235G2-90UT
35/100
PSD4235G2
MEMORY SELECT SIGNALS
The Primary Flash Memory Sector Select (FS0-
FS7), Secondary Flash Memory Sector Select
(CSBOOT0-CSBOOT3) and SRAM Select (RS0)
signals are all outputs of the DPLD. They are de-
fined using PSDsoft Express. The following rules
apply to the equations for these signals:
1.
Primary Flash memory and secondary Flash
memory Sector Select signals must not be
larger than the physical sector size.
2.
Any primary Flash memory sector must not be
mapped in the same memory space as
another Flash memory sector.
3.
A secondary Flash memory sector must not be
mapped in the same memory space as
another secondary Flash memory sector.
4.
SRAM, I/O, and Peripheral I/O spaces must
not overlap.
5.
A secondary Flash memory sector may
overlap a primary Flash memory sector. In
case of overlap, priority is given to the
secondary Flash memory sector.
6.
SRAM, I/O, and Peripheral I/O spaces may
overlap any other memory sector. Priority is
given to the SRAM, I/O, or Peripheral I/O.
Example
FS0 is valid when the address is in the range of
8000h to BFFFh, CSBOOT0 is valid from 8000h to
9FFFh, and RS0 is valid from 8000h to 87FFh.
Any address in the range of RS0 always accesses
the SRAM. Any address in the range of CSBOOT0
greater than 87FFh (and less than 9FFFh) auto-
matically addresses secondary Flash memory
segment 0. Any address greater than 9FFFh ac-
cesses the primary Flash memory segment 0. You
can see that half of the primary Flash memory seg-
ment 0 and one-fourth of secondary Flash memory
segment 0 cannot be accessed in this example.
Also note that an equation that defined FS1 to any-
where in the range of 8000h to BFFFh would not
be valid.
Figure 8 shows the priority levels for all memory
components. Any component on a higher level can
overlap and has priority over any component on a
lower level. Components on the same level must
not overlap. Level 1 has the highest priority and
level 3 has the lowest.
Memory Select Configuration for MCUs with
Separate Program and Data Spaces
The 80C51XA and compatible family of MCUs,
can be configured to have separate address spac-
es for Program memory (selected using Program
Select Enable (PSEN, CNTL2)) and Data memory
(selected using Read Strobe (RD, CNTL1)). Any of
the memories within the PSD can reside in either
space or both spaces. This is controlled through
manipulation of the VM register that resides in the
CSIOP space.
The VM register is set using PSDsoft Express to
have an initial value. It can subsequently be
changed by the MCU so that memory mapping
can be changed on-the-fly.
For example, you may wish to have SRAM and pri-
mary Flash memory in the Data space at Boot-up,
and secondary Flash memory in the Program
space at Boot-up, and later swap the secondary
Flash memory and primary Flash memory. This is
easily done with the VM register by using PSDsoft
Express to configure it for Boot-up and having the
MCU change it when desired.
Table 25 describes the VM Register.
Figure 8. Priority Level of Memory and I/O
Components
Level 1
SRAM, I /O, or
Peripheral I /O
Level 2
Secondary
Non-Volatile Memory
Highest Priority
Lowest Priority
Level 3
Primary Flash Memory
AI02867D
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