參數(shù)資料
型號: PC7410M16
英文描述: PC7410M16 [Updated 12/02. 35 Pages]
中文描述: PC7410M16 [更新12/02。 35頁]
文件頁數(shù): 9/35頁
文件大?。?/td> 361K
代理商: PC7410M16
9
PC7410M16
2183A–HIREL–12/02
Figure 3.
Overshoot/Undershoot Voltage
The PC7410M16 provides several I/O voltages to support both compatibility with exist-
ing systems and migration to future systems. The PC7410M16 “core” voltage must
always be provided at nominal voltage (see Table 3 for actual recommended core volt-
age). Voltage to the L2 I/Os and processor interface I/Os are provided through separate
sets of supply pins and may be provided at the voltages shown in Table 2. The input
voltage threshold for each bus is selected by sampling the state of the voltage select
pins at the negation of the signal HRESET. The output voltage will swing from GND to
the maximum voltage applied to the O
V
DD
or L2O
V
DD
power pins.
Notes:
1. Caution: The input threshold selection must agree with the OV
DD
/L2OV
DD
voltages
supplied.
2. To select the 2.5V threshold option, L2VSEL/BVSEL should be tied to HRESET so
that the two signals change state together. This is the preferred method for selecting
this mode operation.
3. Default voltage setting if left unconnected (internal pull-up). To overcome the internal
pull up resistance, a pull down resistance less than 250
should be used.
Table 2.
Input Threshold Voltage Setting
BVSEL Signal
Processor Bus Input
Threshold is Relative to:
L2VSEL Signal
L2 Bus Input Threshold
is Relative to:
0
(1)
1.8V
0
1.8
HRESET
(1) (2)
2.5V
HRESET
2.5
1
(1)(3)
3.3V
1
2.5
HRESET
3.3V
HRESET
Not supported
Not to exceed
10% of t
SYSCLK
(L2)OV
DD
+ 20%
(L2)OV
DD
+ 5%
(L2)OV
DD
V
IH
V
IL
GND
GND - 0.3V
GND - 0.7V
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