參數(shù)資料
型號(hào)： PC7410M16
英文描述： PC7410M16 [Updated 12/02. 35 Pages]
中文描述： PC7410M16 [更新12/02。 35頁(yè)]
文件頁(yè)數(shù)： 17/35頁(yè)
文件大?。?/td> 361K
代理商： PC7410M16
17
PC7410M16
2183A–HIREL–12/02
Processor Bus AC
Specifications
Table 8 provides the processor AC timing specifications for the PC7410M16 as defined
in Figure 7 and Figure 8.
Notes:
1. All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge of the input
SYSCLK. All output specifications are measured from the midpoint of the rising edge of SYSCLK to the midpoint of the sig-
nal in question. All output timings assume a purely resistive 50
load (see Figure 7). Input and output timings are measured
at the pin; time-of-flight delays must be added for trace lengths, vias and connectors in the system.
2. The symbology used for timing specifications herein follows the pattern of
t
(signal)(state)(reference)(state)
for inputs and t
(reference)(state)(signal)(state)
for outputs. For example, t
IVKH
symbolizes the time input signals
(I) reach the valid state (V) relative to the SYSCLK reference (K) going to the high (H) state or input setup time. And t
KHOV
symbolizes the time from SYSCLK (K) going high (H) until outputs (O) are valid (V) or output valid time. Input hold time can
be read as the time that the input signal (I) went invalid (X) with respect to the rising clock edge (KH) - note the position of
the reference and its state for inputs -and output hold time can be read as the time from the rising edge (KH) until the output
went invalid (OX).
3. The setup and hold time is with respect to the rising edge of HRESET (see Figure 8).
4. This specification is for configuration mode select only. Also note that the HRESET must be held asserted for a minimum of
255 bus clocks after the PLL re-lock time during the power-on reset sequence.
5. t
SYSCLK
is the period of the external clock (SYSCLK) in nanoseconds(ns). The numbers given in the table must be multiplied
by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the parameter in question.
6. Mode select signals are BVSEL, EMODE, L2VSEL, PLL_CFG[0:3].
7. All other output signals are composed of the following - A[0:31], AP[0:3], TT[0:4], TBST, TSIZ[0:2], GBL, WT, CI, DH[0:31],
DL[0:31], DP[0:7], BR, CKSTP_OUT, DRDY, HIT, QREQ, RSRV.
8. Output valid time is measured from 2.4V to 0.8V which may be longer than the time required to discharge from V
DD
to 0.8V.
Table 8.
Processor Bus AC Timing Specifications
(1)
at V
DD
= AV
DD
= 1.8V
±
100 mV;
-55°C
≤
T
j
≤
125°C, OV
DD
= 1.8V
±
100 mV
Symbol
(2)
Parameter
400, 450 MHz
Unit
Min
Max
t
MVRH
(3)(4)(5)(6)
Mode select input setup to HRESET
8
t
SYSCLK
ns
t
MXRH
(2)(3)(5)
HRESET to mode select input hold
0
t
IVKH
Input Setup
1.0
ns
t
IXKH
Input Hold
0
ns
t
KHTSV
t
KHARV
t
KHOV
Output Valid Times:
(7)(8)
TS
ARTRY/SHD0/SHD1
All Other Outputs
3.0
2.3
3.0
ns
t
KHTSX
t
KHARX
t
KHOX
Output Hold Times:
(7)(12)
TS
ARTRY/SHD0/SHD1
All Other Outputs
0.5
0.5
0.5
ns
t
KHOE
(11)
SYSCLK to Output Enable
0.5
ns
t
KHOZ
SYSCLK to Output High Impedance (all except ABB/AMON[0], ARTRY/SHD,
DBB/DMON[0]), SHD0, SHD1)
3.5
ns
t
KHABPZ
(5)(9)(11)
SYSCLK to ABB/AMON[0], DBB/DMON[0] High Impedance after precharge
1.0
t
SYSCLK
t
SYSCLK
t
SYSCLK
t
KHARP
(5)(10)(11)
Maximum Delay to ARTRY/SHD0/SHD1 Precharge
1
t
KHARPZ
(5)(10)(11)
SYSCLK to ARTRY/SHD0/SHD1 High Impedance After Precharge
2
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