參數(shù)資料
型號(hào)： PC7410M16
英文描述： PC7410M16 [Updated 12/02. 35 Pages]
中文描述： PC7410M16 [更新12/02。 35頁(yè)]
文件頁(yè)數(shù)： 26/35頁(yè)
文件大小： 361K
代理商： PC7410M16
26
PC7410M16
2183A–HIREL–12/02
Clock Selection
The PC7410M16’s PLL is configured by the PLL_CFG[0:3] signals. For a given
SYSCLK (bus) frequency, the PLL configuration signals set the internal CPU and VCO
frequency of operation. The PLL configuration for the PC7410M16 is shown in Table 12
for example frequencies.
Notes:
1. PLL_CFG[0:3] settings not listed are reserved.
2. The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core, or VCO
frequencies which are not useful, not supported, or not tested for by the PC7410M16; see “Clock AC Specifications” on
page 16 for valid SYSCLK, core, and VCO frequencies.
3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode
is set for 1:1 mode operation. This mode is intended for factory use only.
Note: The AC timing specifications given in this document do not apply in PLL-bypass mode.
4. In PLL-off mode, no clocking occurs inside the PC7410M16 regardless of the SYSCLK input.
Table 12.
PC7410M16 Microprocessor PLL Configuration
PLL_C
FG[0:3]
Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)
Bus-to-
Core
Multiplier
Core-to-
VCO
Multiplier
Bus
33.3 MHz
Bus
50 MHz
Bus
66.6 MHz
Bus
75 MHz
Bus
83.3 MHz
Bus
100 MHz
Bus
133 MHz
0100
2x
2x
0110
2.5x
2x
1000
3x
2x
400 (800)
1110
3.5x
2x
350 (700)
1010
4x
2x
400 (800)
0111
4.5x
2x
375 (750)
450 (900)
1011
5x
2x
375 (750)
416 (833)
1001
5.5x
2x
366 (733)
412 (825)
1101
6x
2x
400 (800)
450 (900)
0101
6.5x
2x
433 (866)
0010
7x
2x
350 (700)
0001
7.5x
2x
375 (750)
1100
8x
2x
400 (800)
0000
9x
2x
450 (900)
0011
PLL off/bypass
PLL off, SYSCLK clocks core circuitry directly, 1x bus-to-core implied
1111
PLL off
PLL off, no core clocking occurs
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