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參數(shù)資料
| 型號： | PC7410M16 |
| 英文描述： | PC7410M16 [Updated 12/02. 35 Pages] |
| 中文描述： | PC7410M16 [更新12/02。 35頁] |
| 文件頁數(shù)： | 30/35頁 |
| 文件大小： | 361K |
| 代理商： | PC7410M16 |
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30
PC7410M16
2183A–HIREL–12/02
The data bus input receivers are normally turned off when no read operation is in
progress and therefore do not require pull-up resistors on the bus. Other data bus
receivers in the system, however, may require pull-ups, or that those signals be other-
wise driven by the system during inactive periods by the system. The data bus signals
are D[0:63], DP[0:7].
If address or data parity is not used by the system, and the respective parity checking is
disabled through HID0, the input receivers for those pins are disabled, and those pins
do not require pull-up resistors and should be left unconnected by the system. If all par-
ity generation is disabled through HID0, then all parity checking should also be disabled
through HID0, and all parity pins may be left unconnected by the system.
The L2 interface does not normally require pull-up resistors.
JTAG Configuration
Signals
Figure 19.
Suggested TRST Connection
Figure 20.
COP Connector Diagram
Note:
Pins 10, 12 and 14 are no connects. Pin 14 is not physically present.
COP Header
2 k
2 k
PC7410
HRESET
QACK
TRST
HRESET
QACK
From Target
Board Sources
1
2
3
4
5
6
7
8
9
10
11
12
13
15
16
KEY
No pin
T
T
T
T
C
H
S
R
C
V
T
Q
G
Top View
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