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參數(shù)資料
| 型號： | PC7410M16 |
| 英文描述： | PC7410M16 [Updated 12/02. 35 Pages] |
| 中文描述： | PC7410M16 [更新12/02。 35頁] |
| 文件頁數(shù)： | 11/35頁 |
| 文件大?。?/td> | 361K |
| 代理商： | PC7410M16 |
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11
PC7410M16
2183A–HIREL–12/02
L2 Cache Control
Register (L2CR)
The L2 cache control register, shown in Figure 4, is a supervisor-level, implementation-
specific SPR used to configure and operate the L2 cache. It is cleared by hard reset or
power-on reset.
Figure 4.
L2 Cache Control Register (L2CR)
The L2CR bits are described in Table 4.
Table 4.
L2CR Bit Settings
Bit
Name
Function
0
L2E
L2 enable. Enables L2 cache operation (including snooping) starting with the next transaction the L2 cache
unit receives. Before enabling the L2 cache, the L2 clock must be configured through L2CR[2CLK], and the
L2 DLL must stabilize. All other L2CR bits must be set appropriately. The L2 cache may need to be
invalidated globally.
1
L2PE
L2 data parity checking enable. Enables parity generation and checking for the L2 data RAM interface. When
disabled, generated parity is always zeros. L2 Parity is supported by PC7410M16, but is dependent on
application.
2-3
L2SIZ
L2 size — Should be set according to the size of the private memory setting. Total SRAM space is 2M bytes
(256Kx72). See L2 cache/private memory configurations table in Motorola
User's Manual.
4-6
L2CLK
L2 clock ratio (core-to-L2 frequency divider). Specifies the clock divider ratio based from the core clock
frequency that the L2 data RAM interface is to operate at. When these bits are cleared, the L2 clock is
stopped and the on-chip DLL for the L2 interface is disabled. For nonzero values, the processor generates
the L2 clock and the on-chip DLL is enabled. After the L2 clock ratio is chosen, the DLL must stabilize before
the L2 interface can be enabled. The resulting L2 clock frequency cannot be slower than the clock frequency
of the 60x bus interface.
000 L2 clock and DLL disabled
001
÷
1
010
÷
1.5
011
÷
3.5
100
÷
2
101
÷
2.5
110
÷
3
111
÷
4
7-8
L2RAM
L2 RAM type – Configures the L2 RAM interface for the type of synchronous SRAMs used:
Pipelined (register-register) synchronous burst SRAMs that clock addresses in and clock data out
The 7410 does not burst data into the L2 cache, it generates an address for each access.
10 Pipelined (register-register) synchronous burst SRAM - Setting for PC7410M16
9
L2DO
L2 data only. Setting this bit enables údata-only operation in the L2 cache. When this bit is set, only
transactions from the L1 data cache can be cached in the L2 cache. L1 instruction cache operations will be
serviced for instruction addresses already in the L2 cache; however, the L2 cache will not be reloaded for L1
instruction cache misses. Note that setting both L2DO and L2IO effectively locks the L2 cache.
10
L2I
L2 global invalidate. Setting L2I invalidates the L2 cache globally by clearing the L2 status bits. This bit must
not be set while the L2 cache is enabled. See Motorola's User manual for L2 Invalidation procedure.
30
31
L2E
L2SIZ
L2CLK
L2RAM
L2I
L2OH
0000000
L2WT
L2DF
L2FA
L2CLKSTP
L2PE
L2DO
L2CTL
L2TS
L2SL
L2BYP L2HWF L2IO
L2DRO
L2IP
0
1
2
3
4
6
7
8
9
10 11 12 13 14 15 16 17 18
19 20 21 22 23
24
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