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| 型號： | PC7410M16 |
| 英文描述： | PC7410M16 [Updated 12/02. 35 Pages] |
| 中文描述： | PC7410M16 [更新12/02。 35頁] |
| 文件頁數(shù)： | 19/35頁 |
| 文件大小： | 361K |
| 代理商： | PC7410M16 |
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19
PC7410M16
2183A–HIREL–12/02
Figure 7.
AC Test Load for the 60x Interface
Figure 8.
Mode Input Timing Diagram
where VM = Midpoint Voltage (OV
DD
/2)
IEEE 1149.1 AC Timing
Specifications
Table 9
provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure
9, Figure 10, Figure 11 and Figure 12.
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK
to the midpoint of the signal in question. The output timings are measured at the pins.
All output timings assume a purely resistive 50
load (see Figure 9). Time-of-flight
delays must be added for trace lengths, vias and connectors in the system.
2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes
only.
3. Non-JTAG signal input timing with respect to TCK.
4. Non-JTAG signal output timing with respect to TCK.
5. Guaranteed by design and characterization
Z0 = 50 Ohms
RL = 50 Ohms
OV
DD
/2
Output
VM
t
MVRH
t
MXRH
HRESET
MODE SIGNALS
Table 9.
JTAG AC Timing Specifications (Independent of SYSCLK)
(1)
at Recommended
Operating Conditions (see Table 3)
Symbol
Parameter
Min
Max
Unit
f
TCLK
TCK frequency of operation
0
33.3
MHz
t
TCLK
TCK cycle time
30
ns
t
JHJL
TCK clock pulse width measured at OV
DD
/2
15
ns
t
JR
& t
JF
TCK rise and fall times
0
2
ns
t
TRST
(2)
TRST assert time
25
ns
t
DVJH
t
IVJH
(3)
Input Setup Times:
Boundary-scan data
TMS, TDI
4
0
ns
t
DXJH
t
IXJH
(3)
Input Hold Times:
Boundary-scan data
TMS, TDI
20
25
ns
t
JLDV
t
JLOV
(4)
Valid Times:
Boundary-scan data
TDO
4
4
20
25
ns
t
JLDZ
t
JLOZ
(4)(5)
(5)
TCK to output high impedance:
Boundary-scan data
TDO
3
3
19
9
ns
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