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參數(shù)資料
| 型號： | PC7410M16 |
| 英文描述： | PC7410M16 [Updated 12/02. 35 Pages] |
| 中文描述： | PC7410M16 [更新12/02。 35頁] |
| 文件頁數(shù)： | 4/35頁 |
| 文件大?。?/td> | 361K |
| 代理商： | PC7410M16 |
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4
PC7410M16
2183A–HIREL–12/02
AltiVec Unit
–
Full 128-bit data paths
–
Two dispatchable units: vector permute unit and vector ALU unit
–
Contains its own 32-entry 128-bit vector register file (VRF) with six renames
–
The vector ALU unit is further sub-divided into the vector simple integer unit
(VSIU), the vector complex integer unit (VCIU) and the vector floating-point
unit (VFPU).
–
Fully pipelined
Load/Store Unit
–
One-cycle load or store cache access (byte, half-word, word, double-word)
–
Two-cycle load latency with one-cycle throughput
–
Effective address generation
–
Hits under misses (multiple outstanding misses)
–
Single-cycle unaligned access within double-word boundary
–
Alignment, zero padding, sign extend for integer register file
–
Floating-point internal format conversion (alignment, normalization)
–
Sequencing for load/store multiples and string operations
–
Store gathering
–
Executes the cache and TLB instructions
–
Big- and little-endian byte addressing supported
–
Misaligned little-endian supported
–
Supports FXU, FPU, and AltiVec load/store traffic
–
Complete support for all four architecture AltiVec DST streams
Level 1 (L1) Cache Structure
–
32K 32-byte line, 8-way set associative instruction cache (iL1)
–
32K 32-byte line, 8-way set associative data cache (dL1)
–
Single-cycle cache access
–
Pseudo least-recently-used (LRU) replacement
–
Data cache supports AltiVec LRU and transient instructions algorithm
–
Copy-back or write-through data cache (on a page-per-page basis)
–
Supports all PowerPC memory coherency modes
–
Non-blocking instruction and data cache
–
Separate copy of data cache tags for efficient snooping
–
No snooping of instruction cache except for ICBI instruction
Memory Management Unit
–
128 entry, 2-way set associative instruction TLB
–
128 entry, 2-way set associative data TLB
–
Hardware reload for TLBs
–
Four instruction BATs and four data BATs
–
Virtual memory support for up to four petabytes (2
52
) of virtual memory
–
Real memory support for up to four gigabytes (2
32
) of physical memory
–
Snooped and invalidated for TLBI instructions
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