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參數(shù)資料
| 型號： | PC7410M16 |
| 英文描述： | PC7410M16 [Updated 12/02. 35 Pages] |
| 中文描述： | PC7410M16 [更新12/02。 35頁] |
| 文件頁數(shù)： | 5/35頁 |
| 文件大?。?/td> | 361K |
| 代理商： | PC7410M16 |
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5
PC7410M16
2183A–HIREL–12/02
Efficient Data Flow
–
All data buses between VRF, load/store unit, dL1, iL1, L2 and the bus are
128 bits wide
–
dL1 is fully pipelined to provide 128 bits per cycle to/from the VRF
–
L2 is fully pipelined to provide 128 bits per L2 clock cycle to the L1s
–
Up to eight outstanding out-of-order cache misses between dL1 and L2/bus
–
Up to seven outstanding out-of-order transactions on the bus
–
Load folding to fold new dL1 misses into older outstanding load and store
misses to the same line
–
Store miss merging for multiple store misses to the same line. Only
coherency action taken (i.e., address only) for store misses merged to all 32
bytes of a cache line (no data tenure needed).
–
Two-entry finished store queue and four-entry completed store queue
between load/store unit and dL1
–
Separate additional queues for efficient buffering of outbound data (castouts,
write throughs, etc.) from dL1 and L2
Bus Interface
–
MPX bus extension to 60X processor interface
–
Mode-compatible with 60x processor interface
–
32-bit address bus
–
64-bit data bus
–
Bus-to-core frequency multipliers of 2x, 2.5x, 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x,
6.5x, 7x, 7.5x, 8x, 9x supported
–
Selectable interface voltages of 1.8V, 2.5V and 3.3V
Power Management
–
Low-power design with thermal requirements very similar to PC740 and
PC750
–
Low voltage 1.8V processor core
–
Selectable interface voltages of 1.8V can reduce power in output buffers
–
Three static power saving modes: doze, nap, and sleep
–
Dynamic power management
Testability
–
LSSD scan design
–
IEEE 1149.1 JTAG interface
–
Array built-in self test (ABIST) – factory test only
–
Redundancy on L1 data arrays and L2 tag arrays
Reliability and Serviceability
–
Parity checking on 60x and L2 cache buses
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