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參數(shù)資料
| 型號： | PC7410M16 |
| 英文描述： | PC7410M16 [Updated 12/02. 35 Pages] |
| 中文描述： | PC7410M16 [更新12/02。 35頁] |
| 文件頁數(shù)： | 16/35頁 |
| 文件大小： | 361K |
| 代理商： | PC7410M16 |
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16
PC7410M16
2183A–HIREL–12/02
Dynamic Characteristics
After fabrication, parts are sorted by maximum processor core frequency as shown in
“Clock AC Specifications” and tested for conformance to the AC specifications for that
frequency. These specifications are for valid processor core frequencies. The processor
core frequency is determined by the bus (SYSCLK) frequency and the settings of the
PLL_CFG[0:3] signals. Parts are sold by maximum processor core frequency.
Clock AC Specifications
Table 7 provides the clock AC timing specifications as defined in Figure 5.
Notes:
1. Caution: The SYSCLK frequency and PLL_CFG[0:3] settings must be chosen such that the resulting SYSCLK (bus) fre-
quency, CPU (core) frequency and PLL (VCO) frequency do not exceed their respective maximum or minimum operating
frequencies. Refer to the PLL_CFG[0:3] signal description in “Clock Selection” on page 26 for valid PLL_CFG[0:3] settings
2. Rise and fall times for the SYSCLK input measured from 0.4V to 2.4V when OV
DD
= 3.3V nominal.
3. Rise and fall times for the SYSCLK input measured from 0.2V to 1.2V when OV
DD
= 1.8V or 2.5V nominal.
4. Timing is guaranteed by design and characterization.
5. This represents total input jitter, short-term and long-term combined, and is guaranteed by design.
6. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for
PLL lock after a stable V
DD
and SYSCLK are reached during the power-on reset sequence. This specification also applies
when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held
asserted for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.
Figure 5.
SYSCLK Input Timing Diagram
Note:
VM = Midpoint Voltage (OV
DD
/2)
Table 7.
Clock AC Timing Specifications (See Table 3 for Recommended Operating Conditions
)
Symbol
Characteristic
Maximum Processor Core Frequency
Unit
400 MHz
450 MHz
Min
Max
Min
Max
f
CORE
(1)
Processor frequency
350
400
350
450
MHz
f
VCO
(1)
VCO frequency
450
800
450
900
MHz
f
SYSCLK
(1)
SYSCLK frequency
33
133
33
133
MHz
t
SYSCLK
SYSCLK cycle time
7.5
30
7.5
30
ns
t
KR
&
t
KF
t
KR
&
t
KF
t
KHKL
/t
SYSCLK
(2)
SYSCLK rise and fall time
1.0
1.0
ns
(3)
0.5
0.5
ns
(4)
SYSCLK duty cycle measured at OV
DD
/2
SYSCLK jitter
(5)
40
60
40
60
%
±150
±150
ps
Internal PLL relock time
(6)
100
100
μs
SYSCLK
VM
VM
VM
CVIL
CVIH
t
KHKL
t
SYSCLK
t
KR
t
KF
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