- 您現在的位置：買賣IC網 > PDF目錄382376 > PC7410M16 PC7410M16 [Updated 12/02. 35 Pages] PDF資料下載
參數資料
| 型號： | PC7410M16 |
| 英文描述： | PC7410M16 [Updated 12/02. 35 Pages] |
| 中文描述： | PC7410M16 [更新12/02。 35頁] |
| 文件頁數： | 31/35頁 |
| 文件大?。?/td> | 361K |
| 代理商： | PC7410M16 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁當前第31頁第32頁第33頁第34頁第35頁
31
PC7410M16
2183A–HIREL–12/02
Boundary scan testing is enabled through the JTAG interface signals. (BSDL descrip-
tions of the PC7410M16 are available on the Internet at:
www.mot.com/PowerPC/teksupport.).
The TRST signal is optional in the IEEE 1149.1 specification but is provided on all Pow-
erPC implementations. While it is possible to force the TAP controller to the reset state
using only the TCK and TMS signals, more reliable power-on reset performance will be
obtained if the TRST signal is asserted during power-on reset. Since the JTAG interface
is also used for accessing the common on-chip processor (COP) function of PowerPC
processors, simply tying TRST to HRESET is not practical.
The common on-chip processor (COP) function of PowerPC processors allows a remote
computer system (typically a PC with dedicated hardware and debugging software) to
access and control the internal operations of the processor. The COP interface con-
nects primarily through the JTAG port of the processor with some additional status
monitoring signals. The COP port requires the ability to independently assert HRESET
or TRST in order to fully control the processor. If the target system has independent
reset sources, such as voltage monitors, watchdog timers, power supply failures or
push-button switches, then the COP reset signals must be merged into these signals
with logic.
The arrangement shown in Figure 19 allows the COP to independently assert HRESET
or TRST, while ensuring that the target can drive HRESET as well. The pull-down resis-
tor on TRST ensures that the JTAG scan chain is initialized during power-on if a JTAG
interface cable is not attached; if it is attached, it is responsible for driving TRST when
needed.
Table 14.
COP Pin Definitions
Pins
Signal
Connection
Special Notes
1
TDO
TDO
2
QACK
QACK
Add 2K pull-down to ground. Must be merged with on-board QACK, if any.
3
TDI
TDI
4
TRST
TRST
Add 2K pull-down to ground. Must be merged with on-board TRST if any.
See Figure 19.
5
RUN/STOP
No Connect
Used on 604e; leave no-connect for all other processors.
6
VDD_SENSE
VDD
Add 2K pull-up to OV
DD
(for short circuit limiting protection only).
7
TCK
TCK
8
CKSTP_IN
CKSTP_IN
Optional. Add 10K pull-up to OV
DD
. Used on several emulator products. Useful for
checkstopping the processor from a logic analyzer of other external trigger.
9
TMS
TMS
10
N/A
11
SRESET
SRESET
Merge with on-board SRESET, if any.
12
N/A
13
HRESET
HRESET
Merge with on-board HRESET.
14
N/A
Key location; pin should be removed.
15
CKSTP_OUT
CKSTP_OUT
Add 10K pull-up to OV
DD
.
16
Ground
Digital Ground
相關PDF資料 |
PDF描述 |
|---|---|
| PC74HC594P | 8-bit shift register with output register |
| PC74HC594T | 8-bit shift register with output register |
| PC74HCT594P | AMT 2 PORT 1/0-14 SINGLE SIDED CONN |
| PC74HCT594T | 8-bit shift register with output register |
| PC74HCT14 | 10-to-4 line priority encoder |
相關代理商/技術參數 |
參數描述 |
|---|---|
| PC7410MG400LE | 制造商:e2v technologies 功能描述:MPU 7410 RISC 64BIT 0.18UM 400MHZ 1.8V/2.5V/3.3V 360CBGA - Trays |
| PC7410MG400NE | 制造商:e2v technologies 功能描述:MPU 7410 RISC 64BIT 0.18UM 400MHZ 1.8V/2.5V/3.3V 360CBGA - Trays |
| PC7410MG450LE | 制造商:e2v technologies 功能描述:MPU 7410 RISC 64BIT 0.18UM 450MHZ 1.8V/2.5V/3.3V 360CBGA - Trays |
| PC7410MG450NE | 制造商:e2v technologies 功能描述:MPU 7410 RISC 64BIT 0.18UM 450MHZ 1.8V/2.5V/3.3V 360CBGA - Trays |
| PC7410MG500LE | 制造商:e2v Aerospace & Defense 功能描述:MPU 7410 RISC 64-Bit 0.18um 500MHz 1.8V/2.5V/3.3V 360-Pin CBGA 制造商:e2v technologies 功能描述:PC7410MG500LE - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復。