參數(shù)資料
型號: PC7410M16
英文描述: PC7410M16 [Updated 12/02. 35 Pages]
中文描述: PC7410M16 [更新12/02。 35頁]
文件頁數(shù): 21/35頁
文件大?。?/td> 361K
代理商: PC7410M16
21
PC7410M16
2183A–HIREL–12/02
Figure 13.
Test Access Port Timing Diagram
Note:
VM = Midpoint Voltage (OV
DD
/2)
Preparation for
Delivery
Handling
MOS devices must be handled with certain precautions to avoid damage due to accu-
mulation of static charge. Input protection devices have been designed in the chip to
minimize the effect of static buildup. However, the following handling practices are
recommended:
Devices should be handled on benches with conductive and grounded surfaces.
Ground test equipment, tools and operator.
Do not handle devices by the leads.
Store devices in conductive foam or carriers.
Avoid use of plastic, rubber or silk in MOS areas.
Maintain relative humidity above 50% if practical.
For CI-CGA packages, use specific tray to take care of the highest height of the
package compared with the normal CBGA.
TCK
t
JLOX
VM
TDI, TMS
TDO
TDO
VM
Input Data
Valid
t
IVJH
t
IXJH
t
JLOV
t
JLOZ
Output Data Valid
Output Data Valid
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