參數(shù)資料
型號(hào)： PC7410M16
英文描述： PC7410M16 [Updated 12/02. 35 Pages]
中文描述： PC7410M16 [更新12/02。 35頁(yè)]
文件頁(yè)數(shù)： 25/35頁(yè)
文件大?。?/td> 361K
代理商： PC7410M16
25
PC7410M16
2183A–HIREL–12/02
6. Internal pull up on die.
7. OV
DD
supplies power to the processor bus, JTAG, and all control signals except the L2 cache controls (L2CE, L2WE, and
L2ZZ); L2OV
DD
supplies power to the L2 cache I/O interface (L2ADDR (0-18], L2DATA (0-63), L2DP{0-7] and L2SYNC-OUT)
and the L2 control signals; L2AV
DD
supplies power to the SSRAM core memory; and V
DD
supplies power to the processor
core and the PLL and DLL (after filtering to become AV
DD
and L2AV
DD
respectively). These columns serve as a reference for
the nominal voltage supported on a given signal as selected by the BVSEL pin configuration and the voltage supplied. For
actual recommended value of Vin or supply voltages see Recommended Operating Conditions.
8. Output only for 7410, was I/O for 750/755.
9. Enhanced mode only.
10. Deasserted (pulled high) at HRESET for 60x bus mode.
11. Reuses 750/755 DRTRY, DBIS, and TLBISYNC pins (DTI1, DTI2, and EMODE respectively).
12. Unused output in 60x bus mode.
13. Connect to HRESET to trigger post power-on-reset (por) internal memory test.
14. Ignored in 60x bus mode.
15. Not supported on this version.
Figure 15.
Package Dimensions 255 Ball Grid Array
Table 11.
Package Description
Package Outline
21 x 25 mm
Interconnects
255 (16 x 16 ball array less one)
Pitch
1.27 mm
Maximum module height
3.90 mm
Ball diameter
0.8 mm
1 2 3 4 5 6 7 8 9 10 11 1213 14 15 16
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
0.80 (0.032)
BSC
1.27 (0.050)
BSC
19.05 (0.750)
BSC
19.05 (0.750)
BSC
A1 Corner
25.25 (0.994)
MAX
21.21 (0.835)
MAX
2.20 (0.087)
MAX
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