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參數(shù)資料
| 型號(hào)： | PC7410M16 |
| 英文描述： | PC7410M16 [Updated 12/02. 35 Pages] |
| 中文描述： | PC7410M16 [更新12/02。 35頁] |
| 文件頁數(shù)： | 12/35頁 |
| 文件大?。?/td> | 361K |
| 代理商： | PC7410M16 |
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12
PC7410M16
2183A–HIREL–12/02
11
L2CTL
L2 RAM control (ZZ enable). Setting L2CTL enables the automatic operation of the L2ZZ (low-power mode)
signal for cache RAMs. Sleep mode is supported by the
PC7410M16
. While L2CTL is asserted, L2ZZ
asserts automatically when the device enters nap or sleep mode and negates automatically when the device
exits nap or sleep mode. This bit should not be set when the device is in nap mode and snooping is to be
performed through deassertion of QACK.
12
L2WT
L2 write-through. Setting L2WT selects write-through mode (rather than the default write-back mode) so all
writes to the L2 cache also write through to the system bus. For these writes, the L2 cache entry is always
marked as clean (value unmodified) rather than dirty (value modified). This bit must never be asserted after
the L2 cache has been enabled as previously-modified lines can get remarked as clean (value unmodified)
during normal operation.
13
L2TS
L2 test support. Setting L2TS causes cache block pushes from the L1 data cache that result from
dcbf
and
dcbst
instructions to be written only into the L2 cache and marked valid, rather than being written only to the
system bus and marked invalid in the L2 cache in case of hit. This bit allows a
dcbz
/
dcbf
instruction
sequence to be used with the L1 cache enabled to easily initialize the L2 cache with any address and data
information. This bit also keeps
dcbz
instructions from being broadcast on the system and single-beat
cacheable store misses in the L2 from being written to the system bus.
14-15
L2OH
L2 output hold. These bits configure output hold time for address, data, and control signals driven to the L2
data RAMs.
01: 0.8 ms Hold Time - Setting for PC7410M16
16
L2SL
L2 DLL slow. Setting L2SL increases the delay of each tap of the DLL delay line. It is intended to increase the
delay through the DLL to accommodate slower L2 RAM bus frequencies.
0: Setting for PC7410M16
because L2 RAM interface is operated above 100 MHz.
17
L2DF
L2 differential clock. This mode supports the differential clock requirements of late-write SRAMs.
0: Setting for PC7410M16
because late-write SRAMs are not used.
18
L2BYP
L2 DLL bypass is reserved.
0: Setting for PC7410M16
19
L2FA
L2 flush assist (for software flush). When this bit is negated, all lines castout from the dL1 which have a state
of CDMRSV=01xxx1 (i.e. C-bit negated), will not allocate in the L2 if they miss. Asserting this bit forces every
castout from the dL1 to allocate an entry in the L2 if that castout misses in the L2 regardless of the state of
the C-bit. The L2FA bit must be set and the L2IO bit must be cleared in order to use the software flush
algorithm.
20
L2HWF
L2 hardware flush. When the processor detects the value of L2HWF set to 1, the L2 will begin a hardware
flush. The flush will be done by starting with low cache indices and increment these indices for way 0 of the
cache, one index at a time until the maximum index value is obtained. Then, the index will be cleared to zero
and the same process is repeated for way 1 of the cache. For each index and way of the cache, the processor
will generate a castout operation to the system bus for all modified 32-byte sectors. At the end of the
hardware flush, all lines in the L2 tag will be invalidated. During the flush, all memory activity from the icache
and dcache are blocked from accessing the L2 until the flush is complete. Snoops, however, are fully
serviced by the L2 during the flush. When the L2 tags have been fully flushed of all valid entries, this bit will
be reset to b'0" by hardware. When this bit is cleared, it does not necessarily guarantee that all lines from the
L2 have been written completely to the system interface. L2 copybacks can still be queued in the bus
interface unit. Below is the code which must be run to use L2 Hardware Flush. When the final sync
completes, all modified lines in the L2 will have been written to the system address bus.
Disable interrupts
dssall
sync
set L2HWF
sync
Table 4.
L2CR Bit Settings (Continued)
Bit
Name
Function
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