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參數資料
| 型號： | ORT4622 |
| 英文描述： | Field-Programmable System Chip (FPSC) Four-Channel x 622 Mbits/s Backplane Transceiver |
| 中文描述： | 現場可編程系統(tǒng)芯片（促進文化基金）四通道x 622 Mbits /秒背板收發(fā)器 |
| 文件頁數： | 8/90頁 |
| 文件大小： | 1915K |
| 代理商： | ORT4622 |
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8
Lucent Technologies Inc.
ORCAORT4622 FPSC
Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet
March 2000
ORT4622 Overview
Device Layout
The ORT4622 FPSC provides a high-speed backplane
transceiver combined with FPGA logic. The device is
based on a 2.5 V 3.3 V I/O OR3L125B FPGA. The
OR3L125B has a 28 x 28 array of programmable logic
cells (PLCs). For the ORT4622, the bottom ten rows of
PLCs in the array were replaced with the embedded
backplane transceiver core. The ORT4622 embedded
core comprises the HSI macrocell, the synchronous
transport module (STM) macrocell, a CPU interface,
and LVDS I/Os. The four full-duplex channels perform
data transfer, scrambling/descrambling and framing at
the rate of 622 Mbits/s. Figure 1 shows the ORT4622
block diagram.
Table 2
shows a schematic view of the ORT4622. The
upper portion of the device is an 18 x 28 array of PLCs
surrounded on the left, top, and right by programmable
input/output cells (PICs). At the bottom of the PLC
array are the core interface cells (CICs) connecting to
the embedded core region. The embedded core region
contains the backplane transceiver functionality of the
device. It is surrounded on the left, bottom, and right by
backplane transceiver dedicated I/Os as well as power
and special function FPGA pins. Also shown are the
interquad routing blocks (hIQ, vIQ) present in the
Series 3 FPGA devices. System-level functions
(located in the corners of the PLC array), routing
resources, and configuration RAM are not shown in
Table 2
.
Backplane Transceiver Interface
The advantage of the ORT4622 FPSC is to bring spe-
cific networking functions to an early market presence
with programmable logic in FPGA system.
The 622 Mbits/s backplane transceiver core allows the
ORT4622 to communicate across a backplane or on a
given board at an aggregate speed of 2.5 Gbits/s, pro-
viding a physical medium for high-speed asynchronous
serial data transfer between system devices. This
device is intended for, but not limited to, connecting ter-
minal equipment in SONET/SDH and ATM systems.
For networking applications, the ORT4622 offers a
pseudo SONET framer and scrambler/descrambler
interface capable of frame synchronization and inser-
tion/extraction of selectable transport overhead bytes
and SONET scrambling and descrambling for four
STS-12 (622 Mbits/s) channels. The channels are syn-
chronized to each other by a user-provided 8 kHz
frame pulse. The ORT4622 also provides STS-48
(2.5 Gbits/s) operation across all four channels where
each channel is in STS-12 format. The pseudo-SONET
framer of OR4622 is designed with a reduced set of the
SONET framing algorithm. The pointer processing
capability is more suitable for low error rate intersystem
data communication, particular for backplane trans-
ceiver applications. Figure 2 shows the architecture of
the ORT4622 backplane transceiver core.
5-8113(F)
Figure 1. ORCAORT4622 Block Diagram
CLOCK/DATA
RECOVERY
4 FULL-
DUPLEX
SERIAL
CHANNELS
BYTE-
WIDE
DATA
FPGA LOGIC
STANDARD
FPGA
I/Os
LVDS
I/Os
622 Mbits/s
DATA
622 Mbits/s
DATA
STM
POINTER MOVER
SCRAMBLING
FIFO ALIGNMENT
TOH PROCESSOR
HSI
4
4
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