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參數(shù)資料
| 型號： | ORT4622 |
| 英文描述： | Field-Programmable System Chip (FPSC) Four-Channel x 622 Mbits/s Backplane Transceiver |
| 中文描述： | 現(xiàn)場可編程系統(tǒng)芯片（促進(jìn)文化基金）四通道x 622 Mbits /秒背板收發(fā)器 |
| 文件頁數(shù)： | 19/90頁 |
| 文件大?。?/td> | 1915K |
| 代理商： | ORT4622 |
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Lucent Technologies Inc.
Lucent Technologies Inc.
19
Preliminary Data Sheet
March 2000
ORCA ORT4622 FPSC
Four-Channel x 622 Mbits/s Backplane Transceiver
Backplane Transceiver Core Detailed
Description
(continued)
STM Receiver (Backplane -> FPGA)
The ORT4622 has four receiving channels that can be
treated as one STS-48 stream, or treated as indepen-
dent channels. Incoming data is received through
LVDS serial ports at the data rate of 622 Mbits/s. The
receiver can handle the data streams with frame off-
sets of up to ±12 bytes which would be due to timing
skews between cards and along backplane traces. The
received data streams are processed in the HSI and
the STM, and then passed through the CIC boundary
to the FPGA logic.
Framer Block
The framer block, in Figure 5, takes byte-wide data
from the HSI, and outputs a byte-aligned, byte-wide
data stream and 8 kHz sync pulse. The framer algo-
rithm determines the out-of-frame/in-frame status of
the incoming data and will cause interrupts on both an
errored frame and an out-of-frame (OOF) state. The
framer detects the A1/A2 framing pattern and gener-
ates the 8 kHz frame pulse. When the framer detects
OOF, it will generate an interrupt. Also, the framer
detects an errored frame and increments an A1/A2
frame error counter. The counter can be monitored by
a processor to compile performance status on the qual-
ity of the backplane.
Because the ORT4622 is intended for use between it
and another ORT4622 or other devices via a back-
plane, there is only one errored frame state. Thus after
two transitions are missed, the state machine goes into
the OOF state and there is no severely errored frame
(SEF) or loss-of-frame (LOF) indication.
B1 Calculate and Descramble (Backplane -> FPGA)
Each Rx block receives byte-wide scrambled
77.76 MHz data and a frame sync from the framer.
Since each HSI is independently clocked, the Rx block
operates on individual streams. Timing signals required
to locate overhead bytes to be extracted are generated
internally based on the frame sync. The Rx block pro-
duces byte-wide (optionally) descrambled data and an
output frame sync for the alignment FIFO block.
The B1 calculation block computes a BIP-8 (Bit Inter-
leaved Parity 8-bits) code, using even parity over all
bits of the previous STS-12 frame before descram-
bling; this value is checked against the B1 byte of the
current frame after descrambling. A per-stream B1
error counter is incremented for each bit that is in error.
The error counter may be read via the CPU interface.
Descrambling.
The streams are descrambled using a
frame synchronous descrambler of sequence length
127 with a generating polynomial of 1 + x
6
+ x
7
. The
A1/A2 framing bytes, the section trace byte (J0) and
the growth bytes (Z0) are not descrambled. The
descrambling function can be disabled by software.
AIS-L Insertion.
Alarm indication signal (AIS) is a con-
tinuous stream of unframed 1s sent to alert down-
stream equipment that the near-end terminal has
failed, lost its signal source, or has been temporarily
taken out of service. If enabled in the AIS_L force reg-
ister, AIS-L is inserted into the received frame by writ-
ing all ones for all bytes of the descrambled stream.
AIS-L Insertion on Out-of-Frame.
If enabled via a
register, AIS-L is inserted into the received frame by
writing all ones for all bytes of the descrambled stream
when the framer indicates that an out-of-frame condi-
tion exists.
Internal Parity Generation
Even parity is generated on all data bytes and is routed
in parallel with the data to be checked before the pro-
tection switch MUX at the parallel output.
FIFO Alignment (Backplane -> FPGA)
The alignment FIFO allows the transfer of all data to
the system clock. The FIFO sync block (Figure 5)
allows the system to be configured to allow the frame
alignment of multiple slightly varying data streams.
This optional alignment ensures that matching STS-12
streams will arrive at the FPGA end in perfect data
sync. The frame alignment is configurable to allow for
the possibility of fully independent (i.e., total frame mis-
alignment) STS-12s.
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