參數(shù)資料
型號： ORT4622
英文描述： Field-Programmable System Chip (FPSC) Four-Channel x 622 Mbits/s Backplane Transceiver
中文描述： 現(xiàn)場可編程系統(tǒng)芯片（促進(jìn)文化基金）四通道x 622 Mbits /秒背板收發(fā)器
文件頁數(shù)： 41/90頁
文件大?。?/td> 1915K
代理商： ORT4622
Lucent Technologies Inc.
41
Preliminary Data Sheet
March 2000
ORCA ORT4622 FPSC
Four-Channel x 622 Mbits/s Backplane Transceiver
Electrical Characteristics
(continued)
Table 17. Electrical Characteristics for Embedded Core I/O Other than LVDS I/O
Note: All outputs are driving 35 pF, except CPU data bus pins which drive 100 pF. It is assumed that the TTL buffers from the
standard-cell library can handle the 100 pF load.
Symbol
V
IH
V
IL
V
OH
V
OH
Parameter
Min
2.0
—
2.4
—
Max
5.5
0.8
—
0.4
Unit
V
V
V
V
Input High Voltage (TTL input)
Input Low Voltages (TTL input)
Output High Voltage (TTL output)
Output Low Voltage (TTL output)
HSI Circuit Specifications
Input Data
The 622 Mbits/s scrambled input data stream must
conform to SONET STS-12 and SDH STM-4 data for-
mat using either a PN7 or PN9 sequence. The PN7
characteristic is 1 + x
6
+ x
7
and the PN9 characteristic
is 1 + x
4
+ x
9
. The ORT4622 supplies a default scram-
bler using the PN7 sequence. The longest allowable
stream of nontransitional 622 Mbits/s input data is 60
bits. This sequence should not occur more often than
once per minute. An input signal phase change of no
more than 100 ps is allowed over 200 ns time interval,
which translates to a frequency change of 500 ppm.
The signal eye opening must be greater than 0.4 UIp-p
(unit interval peak-to-peak), and the unit interval for
622 Mbits/s is 1.6075 ns.
Jitter Tolerance
The input jitter tolerance of the ORT4622 is shown in
Table 18.
Table 18. Jitter Tolerance
Generated Output Jitter
The generated output jitter is a maximum of 0.2 UIp-p
from 250 kHz to 5 MHz.
PLL
PLL requires an external 10 k
pull-down resistor.
Table 19. PLL
Input Reference Clock
Table 20. Input Reference Clock
Frequency
250 kHz
25 kHz
2 kHz
UIp-p
0.6
6.0
60
Parameter
Min
—
—
10
—
Max
6
2
—
1
Unit
MHz
dB
μs
ms
Loop Bandwidth
Jitter Peaking
Powerup Reset Duration
Lock Acquisition
Parameter
Min
—
—
—
Max
Frequency Deviation
Frequency Change
Phase Change in 200 ns
±
20 ppm
500 ppm
100 ps
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