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| 型號： | ORT4622 |
| 英文描述： | Field-Programmable System Chip (FPSC) Four-Channel x 622 Mbits/s Backplane Transceiver |
| 中文描述： | 現(xiàn)場可編程系統(tǒng)芯片（促進文化基金）四通道x 622 Mbits /秒背板收發(fā)器 |
| 文件頁數(shù)： | 23/90頁 |
| 文件大?。?/td> | 1915K |
| 代理商： | ORT4622 |
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Lucent Technologies Inc.
Lucent Technologies Inc.
23
Preliminary Data Sheet
March 2000
ORCA ORT4622 FPSC
Four-Channel x 622 Mbits/s Backplane Transceiver
Backplane Transceiver Core Detailed
Description
(continued)
Transport Overhead Extraction
Transport overhead is extracted from the receive data
stream by the TOH extract block. The incoming data
gets loaded into a 36-byte shift register on the system
clock domain. This, in turn, is clocked onto the TOH
clock domain at the start of the SPE time, where it can
be clocked out.
During the SPE time, the receiver TOH frame pulse is
generated, RX_TOH_FP which indicates the start of
the row of 36 TOH bytes. This pulse, along with the
receive TOH clock enable, RX_TOH_CK_EN, as well
as the TOH data, are all launched on the rising edge of
the TOH clock TOH_CLK.
TOH Byte Ordering (Backplane to FPGA)
The TOH processor is responsible for dropping all TOH
bytes of each channel through one of four correspond-
ing serial ports. The four TOH serial ports are synchro-
nized to the TOH clock (the same clock that is being
used by the serial ports on the transmitter side). This
free-running TOH clock is provided to the core by
external circuitry and operates at a minimum frequency
of 25 MHz and a maximum frequency of 77.76 MHz.
Data is transferred over serial links in a bursty fashion
as controlled by the Rx TOH clock enable signal, which
is generated by the ASIC and common to the four
channels. All TOH bytes of STS-12 streams are trans-
ferred over the appropriate serial link in the same order
in which they appear in a standard STS-12 frame. Data
transfer should be preformed on a row-by-row basis
such that internal data buffering needs is kept to a min-
imum. Data transfers on the serial links will be synchro-
nized relative to the Rx TOH frame signal.
Receiver TOH Reconstruction
Receiver TOH reconstruction on output parallel bus is
as shown in the following table.
Table 6. Receiver TOH (Output Parallel Bus)
On the TOH serial port, all TOH bytes are dropped as received on the LVDS input (MSB first). The only exception
is the most significant bit of byte A1 of STS#1, which is replaced with an even parity bit. This parity bit is calculated
over the previous TOH frame. Also, on AIS-L (either resulting from LOF or forced through software), all TOH bits
are forced to all ones with proper parity (parity we automatically ends up being set to 1 on AIS-L).
Special TOH Byte Functions
K1 and K2 Handling.
The K1 and K2 bytes are used in automatic protection switch (APS) applications. K1 and K2
bytes can be optionally passed through the pointer mover under software control, or can be set to zero with the
other TOH bytes.
A1 and A2 Handling.
As discussed previously, the A1 and A2 bytes are used for a framing header. A1 and A2
bytes are always regenerated and set to hexadecimal F6 and 28, respectively.
A1
0
0
A1
0
0
A1
0
0
A1
0
0
A1
0
0
A1
0
0
A1
0
0
A1
0
0
A1
0
0
A1
0
0
A1
0
0
A1
0
0
A2
0
0
A2
0
0
A2
0
0
A2
0
0
A2
0
0
A2
0
0
A2
0
0
A2
0
0
A2
0
0
A2
0
0
A2
0
0
A2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
H1
0
0
H1
0
0
H1
0
0
H1
0
0
H1
0
0
H1
0
0
H1
0
0
H1
0
0
H1
0
0
H1
0
0
H1
0
0
H1
0
0
H2
K1
0
H2
0
0
H2
0
0
H2
0
0
H2
0
0
H2
0
0
H2
0
0
H2
0
0
H2
0
0
H2
0
0
H2
0
0
H2
0
0
H3
K2
0
H3
0
0
H3
0
0
H3
0
0
H3
0
0
H3
0
0
H3
0
0
H3
0
0
H3
0
0
H3
0
0
H3
0
0
H3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Regenerated bytes.
Regenerated bytes (under pointer generator control-SS bits must be transparent-AIS-P must be supported).
Bytes taken from Elastic Store Buffer, on negative stuff opportunity-else, forced to all zeros.
Transparent or all zeros (K1/K2 are either taken from K1/K2 buffer or forced to all zeros-soft, control). In transparent mode, AIS-L must be supported.
All zero bytes.
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