參數(shù)資料
型號(hào)： ORT4622
英文描述： Field-Programmable System Chip (FPSC) Four-Channel x 622 Mbits/s Backplane Transceiver
中文描述： 現(xiàn)場(chǎng)可編程系統(tǒng)芯片（促進(jìn)文化基金）四通道x 622 Mbits /秒背板收發(fā)器
文件頁(yè)數(shù)： 4/90頁(yè)
文件大小： 1915K
代理商： ORT4622
ORCAORT4622 FPSC
Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet
March 2000
4
L Lucent Technologies Inc.
Embedded Core Features
(continued)
I
Pseudo-SONET protocol including A1/A2 framing.
I
SONET scrambling and descrambling for required
ones density (optional).
I
Selected transport overhead (TOH) bytes insertion
and extraction for interdevice communication via the
TOH serial link.
FPSC Highlights
I
Implemented as an embedded core in the ORCA
Series 3+ FPSC architecture.
I
Allows the user to integrate the core with up to 120K
gates of programmable logic (all in one device) and
provides up to 242 user I/Os in addition to the
embedded core I/O pins.
I
FPGA portion retains all of the features of the ORCA
Series 3 FPGA architecture:
— High-performance, cost-effective, 0.25 μm, 5-level
metal technology.
— Twin-quad programmable function unit (PFU)
architecture with eight 16-bit look-up tables
(LUTs) per PFU, organized in two nibbles for use
in nibble- or byte-wide functions. Allows for mixed
arithmetic and logic functions in a single PFU.
— Softwired LUTs (SWL) allow fast cascading of up
to three levels of LUT logic in a single PFU.
— Supplemental logic and interconnect cell (SLIC)
provides 3-statable buffers, up to 10-bit decoder,
and PAL*-like AND-OR-INVERT (AOI) in each
programmable logic cell (PLC).
— Up to three ExpressCLK inputs allow extremely
fast clocking of signals on- and off-chip plus
access to internal general clock routing.
— Dual-use microprocessor interface (MPI) can be
used for configuration, as well as for a general-
purpose interface to the FPGA. Glueless interface
to i960
and PowerPC
processors with user-
configurable address space provided.
— Programmable clock manager (PCM) adjusts
clock phase and duty cycle for input clock rates
from 5 MHz to 120 MHz. The PCM may be com-
bined with FPGA logic to create complex
functions, such as digital phase-locked loops,
frequency counters, and frequency synthesizers
or clock doublers. Two PCMs are provided per
device.
— True internal 3-state, bidirectional buses with
simple control provided by the SLIC.
— 32 x 4 RAM per PFU, configurable as single or
dual port. Create large, fast RAM/ROM blocks
(128 x 8 in only eight PFUs) using the SLIC
decoders as bank drivers.
— Built-in boundary scan (IEEE
1149.1 JTAG) and
TS_ALL testability function to 3-state all I/O pins.
I
High-speed, on-chip interface provided between
FPGA logic and embedded core to reduce bottle-
necks typically found when interfacing off-chip.
Software Support
I
Supported by ORCA Foundry software and third-
party CAE tools for implementing ORCA Series 3+
devices and simulation/timing analysis with the
embedded core functions.
I
Embedded core configuration options and simulation
netlists generated by FPSC Configuration Manager
utility.
* PALis a trademark of Advanced Micro Devices, Inc.
i960is a registered trademark of Intel Corporation.
PowerPCis a registered trademark of International Business
Machines Corporation.
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