參數(shù)資料
型號(hào)： ORT4622
英文描述： Field-Programmable System Chip (FPSC) Four-Channel x 622 Mbits/s Backplane Transceiver
中文描述： 現(xiàn)場可編程系統(tǒng)芯片（促進(jìn)文化基金）四通道x 622 Mbits /秒背板收發(fā)器
文件頁數(shù)： 64/90頁
文件大小： 1915K
代理商： ORT4622
ORCAORT4622 FPSC
Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet
March 2000
64
L Lucent Technologies Inc.
Pin Information
(continued)
Table 40. FPSC Function Pin Description
(continued)
* BSCAN pins-TDI, TDO, TCK, and TMS are on FPGA side.
Symbol
I/O
Description
HSI Test Signals
(continued)
tstshftld
I
Enables the test mode control register for shifting in selected tests by a
serial port. Internal pull-down
Enables external test control of 622 MHz clock phase selection. Internal
pull-down
Direction of phase change. Internal pull-down
Moves 622.08 MHz clock selection on phase per positive pulse. Internal
pull-down
Enables 622 Mbits/s loopback mode. Internal pull-down
Controls bypass of 16 PLL-generated phases with 16 low-speed phases.
Internal pull-down
Test mode output port.
ecsel
I
exdnup
etoggle
I
I
loopbken
tstphase
I
I
tstmux[8:0]s
O
CPU Interface Pins
db<7:0>
addr<6:0>
rd_wr_n
cs_n
int_n
MISC System Signals
rst_n
I/O
I
I
I
O
CPU interface data bus. Internal pull-up.
CPU interface address bus. Internal pull-up.
CPU interface read/write. Internal pull-up.
Chip select. Internal pull-up.
Interrupt output. Internal pull-up. Open drain.
I
Reset the Core only. The FPGA logic is not reset by rst_n.
Internal pull-down allows chip to stay in reset state when external driver
loses power.
System clock (77.76 MHz), 50% duty cycle, also the reference clock of PLL.
Internal pull-up.
Temperature sensing diode (anode +).
Temperature sensing diode (cathode –).
sys_clk
I
dxp
dxn
—
—
SCAN and BSCAN Pins*
scan_tstmd
scanen
lvds_en
I
I
I
Scan test mode input. Internal pull-up.
Scan mode enable input. Internal pull-up.
LVDS enable used during BSCAN. During normal operation, lvds_en needs
to be pulled high. lvds_en needs to be pulled low for boundary scan.
Universal BIST Controller Pins
sys_dobist
I
sys_dobist is asserted high to start the BIST, and should be kept high dur-
ing the entire BIST operation. Internal pull-down.
This 32-bit serial out RSB signature consists of the 4-bit FSM state and the
BIST flag flip-flop states from each SBRIC_RS element.
This flag is asserted to one when BIST is complete, and is used for polling
the end of BIST.
sys_rssigo
O
bc
O
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