參數(shù)資料
型號(hào): ORT4622
英文描述: Field-Programmable System Chip (FPSC) Four-Channel x 622 Mbits/s Backplane Transceiver
中文描述: 現(xiàn)場可編程系統(tǒng)芯片(促進(jìn)文化基金)四通道x 622 Mbits /秒背板收發(fā)器
文件頁數(shù): 27/90頁
文件大?。?/td> 1915K
代理商: ORT4622
Lucent Technologies Inc.
Lucent Technologies Inc.
27
Preliminary Data Sheet
March 2000
ORCA ORT4622 FPSC
Four-Channel x 622 Mbits/s Backplane Transceiver
Memory Map
(continued)
Memory Map Overview
Table 9
.
Memory Map
Notes:
1.Generic register block.
2.Device register block-Rx.
3.Device register block-Tx.
ADDR
[6:0]
Reg.
Type
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Default
Value
(hex)
Notes
Generic Register Block
00
sreg
01
sreg
02
sreg
03
creg
04
creg
05
creg
06
preg
fixed rev [7:0]
fixed ID LSB [7:0]
fixed ID MSB [7:0]
scratch pad [7:0]
lockreg MSB [7:0]
lockreg LSB [7:0]
01
01
A0
00
00
00
NA
1
FIFO align-
ment com-
mand
global
reset
command
Device Register Block
08
creg
Rx TOH
frame
and
Rx TOH
clock
enable
control
ext prot
sw en
ext prot
sw
function
STS-48
STS-12 sel
(unused in
ORT4622)
LVDS
lpbk
control
00
2
09
creg
parallel
port out-
put MUX
select for
ch C
FIFO aligner threshold value (min) [4:0]
FIFO aligner threshold value (max) [4:0]
line loop-
back
control
parallel
port out-
put MUX
select for
ch A
serial port
output
MUX
select for
ch C
serial port
output
MUX
select for
ch A
0F
0a
0b
0c
creg
creg
creg
02
15
60
scrambler/
descram-
bler
control
input/
output
parallel
bus parity
control
number of consecutive A1/A2 errors to
generate [3:0]
3
0d
0e
0f
creg
creg
creg
A1 error insert value [7:0]
A2 error insert value [7:0]
transmitter B1 error insert mask [7:0]
00
00
00
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