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參數資料
| 型號： | ORT4622 |
| 英文描述： | Field-Programmable System Chip (FPSC) Four-Channel x 622 Mbits/s Backplane Transceiver |
| 中文描述： | 現(xiàn)場可編程系統(tǒng)芯片（促進文化基金）四通道x 622 Mbits /秒背板收發(fā)器 |
| 文件頁數： | 12/90頁 |
| 文件大?。?/td> | 1915K |
| 代理商： | ORT4622 |
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12
Lucent Technologies Inc.
ORCAORT4622 FPSC
Four-Channel x 622 Mbits/s Backplane Transceiver
Preliminary Data Sheet
March 2000
ORT4622 Overview
(continued)
FPSC Configuration
Configuration of the ORT4622 occurs in two stages,
FPGA bit stream configuration and embedded core
setup.
FPGA Configuration
Prior to becoming operational, the FPGA goes through
a sequence of states, including powerup initialization,
configuration, start-up, and operation. The FPGA logic
is configured by standard FPGA bit stream configura-
tion means as discussed in the Series 3 FPGA data
sheet. Additionally, for the ORT4622, the location of the
CPU interface to the embedded core, either on the
device pins or at the FPGA/embedded core boundary,
is configured via FPGA configuration and is defined via
the ORT4622 design kit. The default configuration sets
the CPU interface pins to be active. A simple micropro-
cessor emulation soft Intellectual Property (IP) core
that uses very small FPGA logic is available from
Lucent. This microprocessor core sets up the embed-
ded core via a state machine and allows the ORT4622
to work in an independent system without an external
microprocessor interface.
Embedded Core Setup
The embedded core operation is set up via the embed-
ded core CPU interface. All options for the operation of
the core are configured according to the device register
map presented in the detailed description section of
this data sheet.
During the powerup sequence, the ORT4622 device
(FPGA programmable circuit and the core) is held in
reset. All the LVDS output buffers and other output
buffers are held in 3-state. All flip-flops in core area are
in reset state, with the exception of the boundry scan
shift registers, which can only be reset by Boundary
Scan Reset. After powerup reset, the FPGA can start
configuration. During FPGA configuration, the
ORT4622 core will be held in reset and all the local bus
interface signals are forced high, but the following
active-high signals (PROT_SWITCH_A,
PROT_SWITCH_C, TX_TOH_CK_EN, SYS_FP,
LINE_FP) are forced low. The CORE_READY signal
sent from the embedded core to FPGA is held low, indi-
cating core is not ready to interact with FPGA logic. At
the end of the FPGA configuration sequence, the
CORE_READY signal will be held low for six SYS_CLK
cycles after DONE, TRI_IO and RST_N (core global
reset) are high. Then it will go active-high, indicating
the embedded core is ready to function and interact
with FPGA programmable circuit. During FPGA recon-
figuration when DONE and TRI_IO are low, the
CORE_READY signal sent from the core to FPGA will
be held low again to indicate the embedded core is not
ready to interact with FPGA logic. During FPGA partial
configuration, CORE_READY stays active. The same
FPGA configuration sequence described previously will
repeat again.
The initialization of the embedded core consists of two
steps: register configuration and synchronization of the
alignment FIFO. In order to configure the embedded
core, the registers need to be unlocked by writing 0xA0
to address 0x04 and writing 0x01 to address 0x05.
Control registers 0x04 and 0x05 are lock registers. If
the output bus of the data, serial TOH port, and TOH
clock and TOH frame pulse are controlled by 3-state
registers (the use of the registers for 3-state output
control is optional; these output 3-state enable signals
are brought across the local bus interface and available
to the FPGA side), the next step is to activate the 3-
state output bus and signals by taking them to func-
tional state from high-impedance state. This can be
done by writing 0x01 to correspond bits of the channel
registers 0x20, 0x38, 0x50, and 0x68. If the 3-state
control is done in FPGA logic or external logic instead
of in the embedded core registers, this step should be
done in that particular control logic also.
In addition, the synchronization of selected streams is
recommended for some networking systems applica-
tions. This is a resync of the alignment FIFO after the
enabled channels have a valid frame pulse. Here are
the procedures: Put all of the streams to be aligned,
including disabled streams, into their required align-
ment mode. Force AIS-L in all streams to be synchro-
nized (refer to register map, write 0x01 to DB1 of
register 0x20, 0x38, 0x50, 0x68). Wait four frames.
Write a 0x01 to the FIFO alignment resync register, bit
DB1 of register 0x06. Wait four frames. Release the
AIS-L in all streams (write 1 to DB1 of register 0x20,
0x38, 0x50, 0x68). This procedures allows normal data
flow through the embedded core.
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