參數(shù)資料
型號(hào): ORT4622
英文描述: Field-Programmable System Chip (FPSC) Four-Channel x 622 Mbits/s Backplane Transceiver
中文描述: 現(xiàn)場(chǎng)可編程系統(tǒng)芯片(促進(jìn)文化基金)四通道x 622 Mbits /秒背板收發(fā)器
文件頁(yè)數(shù): 69/90頁(yè)
文件大?。?/td> 1915K
代理商: ORT4622
Lucent Technologies Inc.
69
Preliminary Data Sheet
March 2000
ORCA ORT4622 FPSC
Four-Channel x 622 Mbits/s Backplane Transceiver
Pin Information
(continued)
The ORT4622 is pin compatible with a Series 3
OR3L125B device in the same package in terms of V
DD
,
V
SS
, con-
figuration, and special function pins. The uses and characteristics of the FPGA user I/O pins in the embedded core
area of the device have changed to support the ORT4622 functionality. Additionally, the lower-left programmable
clock manager (PCM) clock input pin (SECKLL) has been relocated. A "—" indicates the pin is not used and must
be left unconnected (cannot be tied to V
DD
or V
SS
).
Table 43. 432-Pin EBGA Pinout
Pin
E4
D3
D2
D1
F4
E3
E2
E1
F3
F2
F1
H4
G3
G2
G1
J4
H3
H2
J3
K4
J2
J1
K3
K2
K1
L3
M4
L2
L1
M3
N4
M2
N3
N2
P4
N1
P3
P2
ORT4622 Pad
PRD_CFGN
PR1D
PR1C
PR1B
PR1A
PR2D
PR2C
PR2B
PR2A
PR3D
PR3C
PR3B
PR3A
PR4D
PR4C
PR4B
V
DD
2
PR5A
PR6C
PR6A
PR7A
PR8D
PR8C
PR8B
PR8A
PR9D
PR9C
PR9B
PR9A
PR10D
PR10A
PR11D
PR11A
PR12D
PR12C
PR12A
PR13D
PR13C
Function
RD_CFG
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-WR
I/O
I/O
I/O
V
DD
2
I/O
I/O
I/O
I/O-RD/MPI_STRB
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-CS0
I/O
I/O
I/O
I/O-CS1
I/O
I/O
I/O
I/O
I/O
Pin
P1
R3
R2
R1
T2
T4
T3
U1
U2
U3
V1
V2
V3
W1
V4
W2
W3
Y2
W4
Y3
AA1
AA2
Y4
AA3
AB1
AB2
AB3
AC1
AC2
AB4
AC3
AD2
AD3
AC4
AE1
AE2
AE3
AD4
ORT4622 Pad
V
DD
2
PR14D
PR14C
PR14B
PECKR
PR15D
PR15C
PR15B
PR15A
PR16D
PR16B
PR16A
PR17D
PR17A
PR18D
PR18B
PR18A
PR19A
V
DD
2
Function
V
DD
2
I/O
I/O
I/O
I/O-ECKR
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O-M3
I/O
I/O
I/O
M2
V
DD
2
M1
db3 (core)
db2 (core)
db1 (core)
db0 (core)
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