
MT90812
viii
9.0
Timing and Clock Control.............................................................................................24
9.1
9.2
Input Timing Reference..........................................................................................................................25
Serial Data Interface Timing...................................................................................................................26
9.2.1
Local Streams, STi/o0 and STi/o1.................................................................................................. 26
9.2.2
Expansion Bus, EST0/1.................................................................................................................. 26
9.2.3
HMVIP Frame Alignment................................................................................................................ 26
9.2.4
Output Clock and Frame Pulse Signals.......................................................................................... 26
9.2.5
Selecting Timing from the Input Clock Reference or from the PLL ................................................ 27
9.3
Phase Lock Loop (PLL)..........................................................................................................................27
9.3.1
Master and Slave PLL Modes ........................................................................................................ 28
9.4
Watchdog Timer.....................................................................................................................................28
9.5
C8P Pin Timing Source..........................................................................................................................29
9.5.1
Clock Oscillator............................................................................................................................... 29
9.5.2
Crystal Oscillator ............................................................................................................................ 29
10.0 D-Channel Signalling Support .....................................................................................30
11.0 D-Channel Basic Receive Transmit Block...................................................................30
11.1 Receiver Operation ................................................................................................................................31
11.1.1
Receiver Interrupt Handling............................................................................................................ 32
12.0 Transmitter Operation...................................................................................................33
12.1 Transmitter Interrupt Handling................................................................................................................34
13.0 HDLC Resource Allocator Module...............................................................................34
13.1 General Description of MT90812 and Shared HDLC Configuration.......................................................35
13.2 Connection to MT8952 HDLC Controller and MT9171/72B DNIC.........................................................35
13.2.1
Connection to MT8952B HDLC Controller ..................................................................................... 35
13.2.2
Connection to MT9171/72B DNIC.................................................................................................. 36
13.2.3
Data Stream Flow........................................................................................................................... 36
13.3 TX Control..............................................................................................................................................37
13.3.1
Generation of TxCEN..................................................................................................................... 37
13.3.2
End of the Transmission of a Packet.............................................................................................. 38
13.3.3
TX and RX Handshaking................................................................................................................ 38
13.3.4
Merging of D and C-channels......................................................................................................... 39
14.0 RX Control......................................................................................................................39
14.1 RX Circuit Functions...............................................................................................................................39
14.1.1
Generation of RxCEN..................................................................................................................... 40
14.1.2
Dedicated Receive Mode ............................................................................................................... 40
14.1.3
Multiplexed Receive Mode ............................................................................................................. 40
14.1.4
Auto-hunt Monitoring...................................................................................................................... 40
14.1.5
CTS Generation.............................................................................................................................. 41
14.1.6
Circumstances When Monitoring a Channel is Stopped................................................................ 41