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參數(shù)資料
| 型號： | MT90812 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Integrated Digital Switch (IDX)(集成數(shù)字開關(guān)) |
| 中文描述： | 綜合數(shù)字交換機(jī)（IDX的）（集成數(shù)字開關(guān)） |
| 文件頁數(shù)： | 34/105頁 |
| 文件大小： | 334K |
| 代理商： | MT90812 |
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MT90812
Advance Information
30
Figure 20 - Crystal Oscillator Circuit
10.0 D-Channel Signalling Support
The MT90812 can support communications over the D-channel in one of the following methods:
Basic Receive Transmit Method
Shared HDLC Resource Method
The first method is supported by the D-channel Basic Receive Transmit (DBRT) block. The DBRT supports the
communication over the D-channel with the use of start and stop signalling and buffering of messages for both
receive and transmit directions.
The second method supports the use of the MT8952 HDLC Protocol Controller for communication over the D-
Channel. The HDLC Resource Allocator (HRA) block in the MT90812 provides an interface to the MT8952
HDLC Protocol Controller. Refer to the MSAN-122 note for a description of how voice/data channels and
signalling information channels on a digital communications link are supported. MSAN-178 note provides a
programming example for the HRA.
Each of the blocks are described in the following sections.
11.0 D-Channel Basic Receive Transmit Block
The MT90812 can support communications over the D-channel with the use of the D-channel Basic Receiver/
Transmitter (DBRT). The D-Channel Basic Receiver and Transmitter are used to transfer data between a
channel on a serial stream and the parallel micro-port with the use of two 32 byte FIFOs.
There are two modes which the receiver or transmitter may be placed in: Message Length Interrupt Mode
(MLIM) and FIFO Level Interrupt Mode (FLIM). MLI is suited to smaller messages, where efficient use of
bandwidth is important and interrupts are generated on the completion of a message. FLI mode is suited to the
transfer of large amount of data, where due to the size of the message, start, parity and stop bits are required
more often and interrupt generation can support a large data transfer through the FIFO. The bit formatting for
these two modes are summarized in Table 10 and Fig. 21.
In MLI mode a start bit is sent, followed by the message bits and parity (if enabled) and stop bit. In FLI mode
start, parity and stop bits are added to every 8 bits. It is also possible to send unframed data in FLI mode.
The bit rate can be set to 1, 2, or 8 bits per frame for any mode.
OSCo
56pF
1M
39pF
3-50pF
8MHz
MT90812
C8P_C16i
100
1uH
1uH inductor: may improve stability and is optional
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90812AL | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 192 X 192 16.384MBPS 5V 64MQFP - Trays 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 192 X 192 16.384MBPS 5V 64MQFP - Trays |
| MT90812AL1 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 192 X 192 16.384MBPS 5V 64MQFP - Trays 制造商:Microsemi Corporation 功能描述:PB FREE INTEGRATED DIGITAL SWITCH |
| MT90812AP | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Integrated Digital Switch (IDX) |
| MT90812AP1 | 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 192 X 192 16.384MBPS 5V 68PLCC /BAKE/DRYPACK - Rail/Tube 制造商:Zarlink Semiconductor Inc 功能描述:INTEGRATED DIGITAL SWCH |
| MT90812APR | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 192 X 192/64 X 64 1.048GBPS 5V 68PLCC - Tape and Reel |
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