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參數(shù)資料
| 型號： | MT90812 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Integrated Digital Switch (IDX)(集成數(shù)字開關(guān)) |
| 中文描述： | 綜合數(shù)字交換機（IDX的）（集成數(shù)字開關(guān)） |
| 文件頁數(shù)： | 35/105頁 |
| 文件大小： | 334K |
| 代理商： | MT90812 |
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Advance Information
MT90812
31
Table 10 - DBRT Modes of Operation
*X = don’t care
Figure 21 - DBRT modes
11.1
Receiver Operation
The receiver transfers incoming data for a specified channel, identified in CM location 70
H
, to the RX FIFO. The
system read of “D-Channel RX FIFO Output (DRXOUT)” register at 43
H
accesses the next data byte in the RX
FIFO buffer. The following diagram illustrates the data flow for the D-channel data.
The RX control register “D-channel RX FIFO Control Bits (DRXC)” at 41
H
is used to specify the receiver bit
order, data rate at 1, 2 or 8 bits per frame, Message Length or FIFO Level Interrupt Mode, select start and stop
bits, enable parity, and activate the receiver. Refer to page 66 for more description. The receiver bit order
defines whether the first bit received on the TDM channel is the LSB or MSB read on the microport data bus
(D0 or D7, respectively).
In MLI Mode, when the data is transferred to the RX FIFO the start and stop bits are automatically stripped off.
The start and stop enable (SE) bit in DRXC register is not used and the received message (1 to 256 bits) is
always assumed to be framed by the start and stop bits. The received data is only transferred to the RX FIFO
following the reception of the start bit (the first ‘0’). The status of the parity enable (PE) bit in the DRXC register
Mode name
Interrupt
Mode
Mode Bit (M)
Start-Stop
bits
Parity bit
Bit Rate
Message oriented
MLIM
1
X
0
1, 2, or 8
bits/frame
Message oriented
with parity
MLIM
1
X
1
1, 2, or 8
bits/frame
Unframed
FLIM
0
0
x
1, 2, or 8
bits/frame
Byte oriented
FLIM
0
1
0
1, 2, or 8
bits/frame
Byte oriented with
parity
FLIM
0
1
1
1, 2, or 8
bits/frame
ST
STP
ST
STP
B7
B6
B5
B4
B3
B2
B1
B0
B7
B6
B5
B4
B3
B2
B1
B0
B7
B6
B5
B4
B3
B2
B1
B0
B7
B6
B5
B4
B3
B2
B1
B0
ST
P
ST
STP
STP
ST
STP
B7
B6
B5
B4
B3
B2
B1
B0
P
B7
B6
B5
B4
B3
B2
B1
B0
ST
STP
P
MLIM*
MLIM*
FLIM*
FLIM*
FLIM*
Message Oriented
Message Oriented
with Parity
Unframed data
Byte Oriented
Byte Oriented
with Parity
* The bit order can be reversed using RXBO and TXBO in DRXC register
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90812AL | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 192 X 192 16.384MBPS 5V 64MQFP - Trays 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 192 X 192 16.384MBPS 5V 64MQFP - Trays |
| MT90812AL1 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 192 X 192 16.384MBPS 5V 64MQFP - Trays 制造商:Microsemi Corporation 功能描述:PB FREE INTEGRATED DIGITAL SWITCH |
| MT90812AP | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Integrated Digital Switch (IDX) |
| MT90812AP1 | 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 192 X 192 16.384MBPS 5V 68PLCC /BAKE/DRYPACK - Rail/Tube 制造商:Zarlink Semiconductor Inc 功能描述:INTEGRATED DIGITAL SWCH |
| MT90812APR | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 192 X 192/64 X 64 1.048GBPS 5V 68PLCC - Tape and Reel |
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