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參數(shù)資料
| 型號(hào)： | MT90812 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Integrated Digital Switch (IDX)(集成數(shù)字開關(guān)) |
| 中文描述： | 綜合數(shù)字交換機(jī)（IDX的）（集成數(shù)字開關(guān)） |
| 文件頁數(shù)： | 59/105頁 |
| 文件大?。?/td> | 334K |
| 代理商： | MT90812 |
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Advance Information
MT90812
55
22.3
Timing Control Register (TC)
The timing control register is configured as follows:
Read/Write Address is: 002
H
Reset Value is: 20
H
Bit
Name
Description
7
WDE
Watchdog Enable
. When 0, disables the Clock Watchdog Circuit. When 1, the Clock
Watchdog Circuit will generate an interrupt in the event of the loss of the clock at the
C8 input. See “Watchdog Timer” on page 28.
6
FPO
FPO.
Selects ST-Bus or GCI frame alignment and polarity for outgoing frame pulse
generation. When 0, ST-Bus Frame Pulses are generated on F8o and F4o. When 1, GCI
frame pulses are generated and the polarities of C4o and C8 are inverted. The outgoing
frame pulse mode is independent of the incoming frame pulse mode.
5-4
CR1-0
Input Clock Reference.
00 C4
01 C8
10 C8P (default)
11 C16
Selects one of four possible clock references, C4, C8, C8P, or C16. C4 is not valid
when the PLL is not enabled. The MT90812 requires at least an 8M clock internally.
When the C4 input clock is selected the 8.192 Mhz clock is derived from the PLL.
When C8P is selected as the input clock reference no frame pulse is used and the
MT90812 generates F4o and F8o when they are enabled. Refer to Table 9, “Clock
Modes,” on page 25.
3
HMVIP
HMVIP Select.
With C16 as Input Clock Reference, when HMVIP=1, enables the HMVIP
Frame Alignment interface. Otherwise, the device operates in ST-BUS/GCI mode.
2
PE
PLL Enable
. When 0, disables the PLL. When 1, enables the PLL. With the PLL off, C10
is disabled and C4 as an input clock reference is not valid.
1
PMS
PLL Mode Select
. With PE=1, when PMS = 1 the PLL operates in Master Mode.
When PMS = 0, the PLL operates in Slave mode. Default Slave Mode.
0
PCS
PLL Clock Select
. With PE=1, when PCS = 1 selects clocks generated from the PLL
for use in STi/o0, STi/o1 and incoming EST0/1 TDM streams, C2o, F4o and C4o.
Otherwise the clocks are derived directly from the Input Clock Reference. With C4 as
the input clock reference, EST0/1, 4 and 8 Mb/s timing, is generated from the PLL
independent of PCS. Refer to Table 9, “Clock Modes,” on page 25 and Section 9.2.5.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90812AL | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 192 X 192 16.384MBPS 5V 64MQFP - Trays 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 192 X 192 16.384MBPS 5V 64MQFP - Trays |
| MT90812AL1 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 192 X 192 16.384MBPS 5V 64MQFP - Trays 制造商:Microsemi Corporation 功能描述:PB FREE INTEGRATED DIGITAL SWITCH |
| MT90812AP | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Integrated Digital Switch (IDX) |
| MT90812AP1 | 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 192 X 192 16.384MBPS 5V 68PLCC /BAKE/DRYPACK - Rail/Tube 制造商:Zarlink Semiconductor Inc 功能描述:INTEGRATED DIGITAL SWCH |
| MT90812APR | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 192 X 192/64 X 64 1.048GBPS 5V 68PLCC - Tape and Reel |
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