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參數(shù)資料
| 型號(hào)： | MT90812 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Integrated Digital Switch (IDX)(集成數(shù)字開關(guān)) |
| 中文描述： | 綜合數(shù)字交換機(jī)（IDX的）（集成數(shù)字開關(guān)） |
| 文件頁數(shù)： | 32/105頁 |
| 文件大?。?/td> | 334K |
| 代理商： | MT90812 |
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MT90812
Advance Information
28
9.3.1
The PLL Master/Slave (PMS) bit in the TC register selects the PLL mode. In Master mode the PLL loop filter is
selected to minimize the magnitude of any one clock correction. This preserves the C10o 40/60 duty cycle
given the input jitter as specified on page 95. For example this provides the 10.24 MHz clock required for DNIC
operation with up to 32ns of clock correction on the input clock once per 125us frame. Refer to Intrinsic Jitter
for Master and Slave modes on page 93 and typical Input to Output Jitter Transfer for Master Mode on page 93.
Master and Slave PLL Modes
In Slave mode the PLL loop filter is selected to minimize the phase delay on the output clock with respect to the
input clock reference. The typical Input to Output Jitter Transfer for Slave Mode is shown on page 94. In Slave
mode the Loop Filter ensures a phase difference of less than 15 ns. This is assuming an input clock reference
from the Master IDX, where the Master IDX has up to 32 ns of clock correction on the input clock once per 125
us. In an application where the clock reference does not require jitter attenuation the PLL can be used in Slave
mode. For example in a multi-IDX application the Master IDX could have its PLL in Master Mode, and generate
clocks for the other IDX devices. Setting the PLLs of these Slave IDX devices in Slave mode lessens phase
delay while taking advantage of the clock source from the Master IDX. Note: the Master IDX PLL maybe placed
in Slave mode as well if jitter attenuation is not required.
9.4
Watchdog Timer
A watchdog timer monitors C8 input. This requires the presence of a 8.192 MHz clock at C8P_C16. In the
event of the loss of the C8 clock an interrupt is generated and the C8F bit in the Interrupt Status Register
(INTS) is set. The system can service the interrupt and maintain operation of the MT90812 by switching clock
input reference from C8 (CR0-1=01) to C8P (CR0-1=10) and enable the MT90812 to supply C8 output.
Figure 18 - Watchdog Configuration
This provides redundancy for the clock source in a multiple IDX system. The watchdog timer is enabled by
setting WDE bit in Timing Control Register (TC).The interrupt is enabled by setting C8FE bit in Interrupt Enable
Register (INTE).
STi0
STi1
STo0
STo1
IDX A
C4i
F4i
C8
F8
F4o
C4o
C10o
C8P OSCo
EST0
EST1
IDX B
C8P OSCo
Crystal
8.192 MHz
Crystal
8.192 MHz
STi0
STi1
STo0
STo1
C4i
F4i
C8
F8
F4o
C4o
C10o
EST0
EST1
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90812AL | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 192 X 192 16.384MBPS 5V 64MQFP - Trays 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 192 X 192 16.384MBPS 5V 64MQFP - Trays |
| MT90812AL1 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 192 X 192 16.384MBPS 5V 64MQFP - Trays 制造商:Microsemi Corporation 功能描述:PB FREE INTEGRATED DIGITAL SWITCH |
| MT90812AP | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Integrated Digital Switch (IDX) |
| MT90812AP1 | 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 192 X 192 16.384MBPS 5V 68PLCC /BAKE/DRYPACK - Rail/Tube 制造商:Zarlink Semiconductor Inc 功能描述:INTEGRATED DIGITAL SWCH |
| MT90812APR | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 192 X 192/64 X 64 1.048GBPS 5V 68PLCC - Tape and Reel |
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