- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383645 > MT90812 (Mitel Networks Corporation) Integrated Digital Switch (IDX)(集成數(shù)字開關(guān)) PDF資料下載
參數(shù)資料
| 型號： | MT90812 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Integrated Digital Switch (IDX)(集成數(shù)字開關(guān)) |
| 中文描述： | 綜合數(shù)字交換機（IDX的）（集成數(shù)字開關(guān)） |
| 文件頁數(shù)： | 51/105頁 |
| 文件大小： | 334K |
| 代理商： | MT90812 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁當前第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁
Advance Information
MT90812
47
Subsequently the interrupt occur once every 8 bits (53 1/3 frames). Wait until the desired number of
channel seizure bits have been sent.
Transmit Mark
3.
Switch to mark as the idle state. Again use end of transmission interrupt to count the number of
mark bits. When switching the idle state the interrupt bit count is not affected, i.e. the bit count is not
restarted but will interrupt 8 bit times after the last interrupt. Wait until the desired number of mark
bits have been sent.
Transmit Data Packet
4.
Select FIFO empty interrupt. End of transmission interrupt is disabled by the selection. Even though
the FIFO is empty there will be no interrupt because the empty interrupt occurs only when the FIFO
is read to empty, not when it is emptied via FIFO clear. Write to FIFO for up to 20 bytes. The first
byte will be sent on the next bit boundary or the one after depending on when the byte is written.
5.
When FIFO empty interrupts, reload FIFO. Repeat as necessary until the entire message has been
sent. When the FIFO empty interrupts, there are 11 bit times (73 1/3 frames) before idle state
transmission will commence.
End Transmission
6.
After the FIFO has been loaded for the last time, switch to end of transmission interrupt. Select
mark as the idle state.
7.
Wait for end of transmission interrupt which occurs after 2 idle state bits have been sent after the
stop bit of the last FIFO byte. If the system does not disable FSK via FEN=0, end of transmission
will interrupt again once every 8 bit times.
18.0 Ringing Generator
A Ringing Generator is provided on pins R+ and R-. The output are two square waves 180 degrees out of
phase. The frequency is selected with bits F1,F0 in Ringer and FSK Control Register (RFC) and can be 16, 20,
25 or 50 Hz. Setting the bit RE to “0” in the same register tri-states the drivers for both pins R+ and R-.
19.0 Supervisory Signal Detection and Cadence Measurement
Two energy detect blocks, A and B, are provided for monitoring supervisory signalling during trunk calls. Each
of energy detect blocks can be assigned to an incoming channel, by programming one of the two Connect
Memory Low locations 70
H
and 71
H
. A low and high threshold level is programmed in the Energy Detect Low
and High Threshold Registers (EDLTA/B or EDHTA/B). The Energy Detect blocks are enabled by setting ENA
or ENB bits in the Tone Generation and Energy Detect Control Register (TEDC) described on page 61.
The energy detect is implemented using a peak detector with an exponential attack and decay time constant of
2 msec and a 25 msec “l(fā)eaky” hold time to bridge between the envelope peaks. The peak detector decays
exponentially following the hold time limit.
Supervisory signalling cadence measurement is illustrated in Fig. 27. A counter is used to time the cadence of
the signal. When the signal envelope crosses the energy detect high threshold at point A, the counter value,t0,
is transferred to the SSCR register and the counter is reset and starts counting the next interval. The position
of the signal envelope, now above the high threshold, is indicated with bit 7 of SSCR (also labelled the P bit)
set to 1. An interrupt is generated and the energy detect bit in the Interrupt Status Register (INTS) is set.
At point B the low threshold limit is crossed, the SSCR register is updated with the new count, t1, and an
interrupt is generated. The position of the signal envelope, now below the low threshold, is indicated with the P
bit of SSCR set to 0.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90840AK | Distributed Hyperchannel Switch |
| MT90840AP | Distributed Hyperchannel Switch |
| MT9085B | PAC - Parallel Access Circuit(并行存取電路) |
| MT9092 | Digital Telephone with HDLC(數(shù)字電話（帶高階數(shù)據(jù)鏈路控制HDLC）) |
| MT9092 | ISO2-CMOS ST-BUS⑩ FAMILY Digital Telephone with HDLC (HPhone-II) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90812AL | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 192 X 192 16.384MBPS 5V 64MQFP - Trays 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 192 X 192 16.384MBPS 5V 64MQFP - Trays |
| MT90812AL1 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 192 X 192 16.384MBPS 5V 64MQFP - Trays 制造商:Microsemi Corporation 功能描述:PB FREE INTEGRATED DIGITAL SWITCH |
| MT90812AP | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Integrated Digital Switch (IDX) |
| MT90812AP1 | 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 192 X 192 16.384MBPS 5V 68PLCC /BAKE/DRYPACK - Rail/Tube 制造商:Zarlink Semiconductor Inc 功能描述:INTEGRATED DIGITAL SWCH |
| MT90812APR | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 192 X 192/64 X 64 1.048GBPS 5V 68PLCC - Tape and Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。