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| 型號(hào)： | IBM3288H2848 |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁(yè)數(shù)： | 98/131頁(yè) |
| 文件大小： | 1679K |
| 代理商： | IBM3288H2848 |
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PRS28.4G
IBM Packet Routing Switch
I/O Definitions and Timing
Page 98 of 131
prs28.03.fm
August 31, 2000
TCK
Input
Test Clock Input - see
IEEE 1491.1 Specification “IEEE Standard Test Access Port
and Boundary Scan Architecture”
on page 131 [1] for details.
TMS
Input
Test Mode Select Input. See [1].
TDI
Input
Test Data Input. See [1].
TDO
Output
Test Data Output. See [1].
TRST
Input
Test Reset Input. See [1].
Must be asserted during a Power-On-Reset to reset the JTAG control logic.
IOTEST
Input
Used for Reduced Pin Count Testing. It allows all LSSD boundary inputs to drive sig-
nals out (this makes all boundary OCRs and CIOs).
Test (LSSD) Interface Signals
LSSD_SCAN_MODE
Input
Allows all clocks to be controlled from the primary inputs and connects all scan
chains. This signal must be set to ‘0’b during normal operation and to ‘1’b during
LSSD test.
LSSD_SCAN_GATE
Input
Controls the functional clock for special logic books.
LSSD_A_CLK
Input
Used as an external source for the internal SRL scan A clock. It is used during LSSD
test to enable the tester to source the internal SRL clocks independently of the pri-
mary inputs.
This signal must be ‘1’b (pull-up) during normal operation.
LSSD_B_CLK
Input
Used as an external source for the internal SRL scan B clock. It is used during LSSD
test to enable the tester to source the internal SRL clocks independently of the pri-
mary inputs. This signal must be ‘1’b (pull-up) during normal operation
LSSD_B2_CLK
Input
Used as an external source for some internal SRL scan B clock. It is used during
LSSD test to enable the tester to source the internal SRL clocks independently of the
primary inputs. This signal must be ‘1’b (pull-up) during normal operation.
LSSD_C1_CLK
Input
Used as an external source for the internal SRL scan C clock. It is used during LSSD
test to enable the tester to source the internal SRL clocks independently of the pri-
mary inputs. This signal must be ‘1’b (pull-up) during normal operation.
LSSD_C2_CLK
Input
Used as an external source for the internal GRA and RAM scan C clock. It is used
during LSSD test to enable the tester to source the internal GRA clocks indepen-
dently of the primary inputs. This signal must be ‘1’b (pull-up) during normal operation.
LSSD_C3_CLK
Input
Used as an external source for the second write port for internal dual port GRA scan C
clock. It is used during LSSD test to enable the tester to source the internal GRA
clocks independently of primary inputs. This signal must be ‘1’b (pull-up) during nor-
mal operation.
SCAN_IN(0:14)
Input
Data input for the LSSD scan operation.
SCAN_OUT(0:14)
Output
Data output for the LSSD scan operation.
LSSD_TAP_C1
Input
LSSD Tap Controller C1 clock.
LSSD_TAP_C2
Input
LSSD Tap Controller C2 clock
nDI1
Input,
active low
Serves as the driver inhibit for all chip non-test outputs. When a low level (`0'b) is
applied to this input, all chip non-test outputs are disabled. When this signal is inactive
(`1'b), all on-test outputs are controlled by the functional enable.
This input enables exclusive control of the non-test outputs independently of their
respective functional enable, for the purpose of LSSD test.
Table 21: Signal Definitions
(Page 5 of 6)
Signal Name
Type
Description
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PDF描述 |
|---|---|
| IBM32NPR100EXXCAB133 | Microprocessor |
| IBM32NPR101EPXCAC133 | Microprocessor |
| IBM37RGB524CF17A | Video DAC with Color Palette (RAMDAC) |
| IBM37RGB524CF22A | Video DAC with Color Palette (RAMDAC) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IBM32NPR100EXXCAB133 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| IBM32NPR101EPXCAC133 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor |
| IBM35CPC945C03C-2 | 制造商:IBM 功能描述: |
| IBM37RGB524CF17A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
| IBM37RGB524CF22A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC) |
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