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參數(shù)資料
| 型號(hào)： | IBM3288H2848 |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁數(shù)： | 49/131頁 |
| 文件大?。?/td> | 1679K |
| 代理商： | IBM3288H2848 |
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PRS28.4G
IBM Packet Routing Switch
prs28.03.fm
August 31, 2000
Programming Interface and Internal Registers
Page 49 of 131
4.1.3 OCM Response Register
The OCM Response Register is a 17 bit register. The Response Register is physically the same register as
the Instruction Register, except that the Response Register uses only the 17 least significant bits of the
Instruction Register. Each OCM instruction causes the Response Register(1:16) to be loaded with 16 bits of
instruction specific data. The Response register logic generates odd parity over the 16 bits of instruction
specific data and loads this into Response Register(0).
The Response Register is shifted out the EMB_DATA_OUT pin during the following instruction operation,
beginning with bit 16 (LSB).
4.1.4 OCM Error Checking
OCM error checking consists of one bit of parity protection for each instruction scanned into the Instruction
Register. If a parity error is detected on a received instruction, the execution of that instruction is inhibited and
bit 0 is set in the Status Register. The Response Register is not loaded when a parity error is detected in the
Instruction Register.
The number of bits in the instruction protected by the parity bit depends on the contents of the Op Code field
of the Instruction Register. When the number of instruction bits protected by the parity bit is less than 24, the
bits protected by the parity bit are always the most significant bits. The table below shows the number of
instruction bits protected by the parity bits given the Op Code.
Note that only the number of protected bits has to be shifted into the Instruction Register. This mean, for
instance, that a Read command will shift 8 bits, and the response is shifted out by a NOOP command that
takes 16 bits.
P
Instruction Specific Data
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
Table 14: Number of Instruction Bits Protected by Parity Bit
Op Code
Number of Bits Protected
NOOP
16
ECHO
24
WRITE REGISTER
24
READ REGISTER
8
EVENT
24
RESET
8
READ STATUS
8
OCD ENABLE/DISABLE
24
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