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參數(shù)資料
| 型號： | IBM3288H2848 |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁數(shù)： | 17/131頁 |
| 文件大?。?/td> | 1679K |
| 代理商： | IBM3288H2848 |
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PRS28.4G
IBM Packet Routing Switch
prs28.03.fm
August 31, 2000
Architecture
Page 17 of 131
Incoming packets are sorted by priority when stored, according to a priority flag they carry. The highest
priority is represented by 0 and the lowest by 3. Packets are transmitted on a given output with the highest
available priority, always overtaking the lower priorities.
2.1.3 Flow Control
Flow control is provided by the output queue, as well as for the entire shared memory.
One threshold value is associated with all logical queues (of each output). Each output queue has one unique
counter. The total number of packets in all four logical queues of one output is compared to the threshold
value of a given priority, in order to provide flow control for that output priority.
In addition, one counter keeps track of the total number of packets in shared memory. The shared memory
also has four thresholds, one per priority. The total number of packets in shared memory is compared to
these threshold values for each priority, regardless of the output destination of the packets.
2.1.4 Multicast
The internal architecture of the island allows for packets, physically stored once in shared memory, to be
multicasted to multiple outputs. A multicast packet is transmitted on the output ports according to the FIFO
structure of each destination output queue (not necessarily at the same time on all ports). Multicast packets
can only have one priority for all of its destinations.
2.1.5 Control Packets
Support is provided for receiving packets destined to a local processor, and for transmitting packets
constructed by a local processor. These packets are known as Control Packets.
A 16-position FIFO queue is provided for incoming control packets (no priority is involved).
2.1.6 Incoming Flow Process
Each incoming packet carries information about the physical output addresses (output port) of its destina-
tions, the logical address (priority) per output, or all zero (identification as a control packet).
The island controller allows one packet, corresponding to one input, to be processed and stored at a time.
Inputs are visited once per sequencer cycle. When the input on which a packet arrives is visited by the island
controller, the packet data is stored once in the shared memory. The address of this location is placed in the
logical queues (specified by its priority) of all of its destination outputs according to its priority. At the same
time, the shared memory counter and the output queue counters of its destination are incremented.
If an incoming packet is marked as a control packet, it is also stored in shared memory. Its address is then
placed in a control packet queue, and an interrupt is sent to the local processor. An incoming control packet
can only be received if fewer than 16 control packets are present in the control packet queue. Otherwise, the
packet is discarded and a flag is raised.
2.1.7 Incoming Flow Control
Flow control of incoming packets is provided by grants which are authorizations for the attached adapter to
transmit a packet. Grants are provided separately for each output port and for each priority of a port. An
output queue grant for a priority is provided whenever the total packet count for an output (regardless of
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