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| 型號(hào)： | IBM3288H2848 |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁(yè)數(shù)： | 96/131頁(yè) |
| 文件大?。?/td> | 1679K |
| 代理商： | IBM3288H2848 |
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PRS28.4G
IBM Packet Routing Switch
I/O Definitions and Timing
Page 96 of 131
prs28.03.fm
August 31, 2000
Master-Slave Speed Expansion Signals
The following I/Os are only connected when two devices are in external speed expansion.
Note that these signals are synchronous to the internal master/slave clocks and point to point between the two devices.
MS_SYNC_OUT
Output
Connects directly to the MS_SYNC_IN pin of the other device. When the device is
master, this signal is a synchronous one clock cycle (of 9 to 10ns) pulse to frame the
information that is multiplexed on the MS_IN_ADDR(0:10) and
MS_OUT_ADDR(0:10) busses.
When the device is slave, this signal has no function, but it has to be connected.
When the device is used alone, that is, without external speed expansion, this signal
is tri-stated.
MS_SYNC_IN
Input
Connects directly to the MS_SYNC_OUT of the other device.
MS_DASLSYNC_OUT(0:1)
Output
Directly connected to the MS_DASLSYNC_IN bus of the other device in speed expan-
sion (no function).
MS_DASLSYNC_IN(0:1)
Input
Connects directly to the MS_DASLSYNC_OUT of the other device in speed expan-
sion.
MS_IN_ADDR(0:10)
Bidirec-
tional
Goes from the master to the slave. In single device mode, this bus is tri-stated. It pro-
vides the address used by the input controllers to store the next packet.
MS_IN_ADDR(0:8) are the 9-bit wide address value fields, MS_IN_ADDR(9) is the
valid bit of the address, and MS_IN_ADDR(10) is the odd parity bit over
MS_IN_ADDR(0:9). MS_IN_ADDR(0:10) is a multiplexed bus on which the store
addresses of all 16 input controllers are transmitted. It is synchronized with
MS_SYNC_OUT. When MS_SYNC_OUT is high, the address for port 0 is carried.
N
clock cycles after MS_SYNC high, the address for port
N
is carried.
Note that the values of the address and the valid bit are used by the master to indicate
to the slave ports, according to the table below, whether to ignore the incoming data
packet, to receive the incoming data packet, or to treat the incoming packet as idle.
The slave action is as follows:
Bits 0-8 (Address)Bit 9 (Valid Bit)Slave Action
Zero value1
Ignore the data packet
Non Zero value1Receive the data packet
-
0
Treat incoming packet as an Idle Packet
MS_OUT_ADDR(0:10)
Bidirec-
tional
Goes from the master to the slave. In single device mode, this bus is tri-stated. It pro-
vides the address used by the output controllers to read the next packet.
MS_OUT_ADDR(0:8) are the 9-bit wide address value fields, MS_OUT_ADDR(9) is
the valid bit of the address, and MS_OUT_ADDR(10) is the odd parity bit over
MS_OUT_ADDR(0:9). MS_OUT_ADDR(0:10) is a multiplexed bus on which the read
addresses of all 16 output controllers are transmitted. It is synchronized with
MS_SYNC_OUT. When MS_SYNC_OUT is high, the address for port 0 is carried.
N
clock cycles after MS_SYNC_OUT high, the address for port
N
is carried.
OCM Interface Signals
EMB_A_CLOCK
EMB_B_CLOCK
Inputs (2)
Free-running clock signals that generate the OCM internal C (EMB_A_CLOCK) and B
(EMB_B_CLOCK) clocks. The clock frequency must be less than or equal to half of
the internal byte clock frequency (100 to 111.1 MHz).
The EMB_A_CLOCK and the EMB_B_CLOCK must be non-overlapping clocks; that
is, they cannot be high at the same time (See
I/O Definitions and Timing
on page 94).
For scan operation, these signals are sampled by the system clock.
nEMB_SIGOUT
Output
active low
Used to generate an interrupt to the microprocessor. The signal remains asserted
until an OCM_READ_STATUS command occurs. To support a wired-OR configura-
tion, nEMB_SIGOUT uses an open-drain driver and is in the high-impedance state
when inactive.
EMB_DATA_IN
Input
Serial data line that shifts into the OCM either the instruction or the scan string data,
according to EMB_MODE and based on the EMB clock.
Table 21: Signal Definitions
(Page 3 of 6)
Signal Name
Type
Description
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