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| 型號(hào)： | IBM3288H2848 |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁(yè)數(shù)： | 93/131頁(yè) |
| 文件大?。?/td> | 1679K |
| 代理商： | IBM3288H2848 |
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PRS28.4G
IBM Packet Routing Switch
prs28.03.fm
August 31, 2000
Reset, Initialization, and Operation
Page 93 of 131
6. Issue a Free Current Control Packet Address command via the Table Command Register to free up the
first address in the Control Packet Queue.
7. If the Control Packet Counter is not zero, and/or if another Control Packet Received Interrupt is issued,
perform all above items again.
For external speed expansion, the shared memory start address of the control packet for the slaves is the
same as for the master. Therefore, after issuing the Load Next Control Packet Address command to the
master, the local processor has to read the master Memory Row Address register and write its content to the
slave Memory Row Address Register. The local processor then has to issue the Read Command to the slave,
followed by the Read Command to the master. Only then can the data from the slave and the master be read.
Once the first row is completely read in both master and slave, the same sequence of Read Command to the
slave and the master has to be issued in order to read the second data row in both devices. This is necessary
to guarantee the access time to the slave chip shared memory. All rows in both the master and the slave have
to be read before issuing the Free Current Control Packet Address command to the master.
6.5.2 Control Packet Transmission
Control Packets are sent one at a time. Note that Control Packets can only start at shared memory location
zero. In order to transmit a Control Packet, the following tasks are performed:
1. Load the Memory Row Address Register with value zero.
2. Build the first row of the control packet in the Memory Row Register via the Table Pointer and Table Data
registers.
3. Issue a Memory Row Write command via the Command Register to load the row into shared memory.
4. Update Memory Row Address Register to point to the location where the next row of the packet has to go,
and repeat steps 2 and 3 for all rows of the Control Packet.
5. Specify the output ports which the Control Packet has to be transmitted from, by loading the Control
Packet Destination Register.
6. Issue a Control Packet Transmit command via the Command Register. Wait for a Control Packet Transmit-
ted Interrupt.
For external speed expansion, the local processor must write the rows to the slave and the master devices
before issuing the Control Packet Transmit command. The local processor must first write a row to the slave
device, followed by a row to the master. This sequence is necessary to guarantee access time to the slave
memory.
Note:
The Control Packet Destination Register must be specified only for the master device.
1
0
128 to 160
A and A+1
Table 20: Master and Slave Memory Bank Addressing
External Speed Expansion
Internal Speed Expansion
Packet Size
(Number of bytes)
Addresses to read in master
and slave memory banks
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