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參數(shù)資料
| 型號： | IBM3288H2848 |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁數(shù)： | 89/131頁 |
| 文件大小： | 1679K |
| 代理商： | IBM3288H2848 |
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PRS28.4G
IBM Packet Routing Switch
prs28.03.fm
August 31, 2000
Reset, Initialization, and Operation
Page 89 of 131
After configuration of the PLL Register (if necessary depending on use of internal or external PLL), the Clock
Start OCM Event is sent. This event causes the PLL Reset to be internally released when the internal PLL is
enabled. 100 microseconds after the PLL Reset has been released, the high speed DASL logic is automati-
cally placed in reset. If the internal PLL is not enabled, the DASL logic reset is sent just after the Clock Start
Event. After the DASL logic has been reset, the reset of the Clock/BIST/Flush-Reset is released, which
causes the internal Flush-Reset sequence to begin. The Status Register must be polled to determine when
the flush reset is complete.
In summary, the following steps must be taken to complete a Power-On-Reset of the device:
1. Assert nRESET for at least four EMB clock cycles.
2. Program the PLL Tune Bits via the PLL Register,
only
when using the internal PLL.
3. Issue a Clock Start OCM Event.
Check the Status Register bit 15 for completion of the Reset and Flush-Reset sequence. The first Response
to an OCM command after reset is undefined. Therefore, this data must be discarded and no checks
(including parity) should be performed on the first OCM Response.
6.2.2 Flush Reset and OCM_RESET Command
As mentioned above, the flush reset sequence is triggered automatically after a Power On Reset (nRESET)
and Clock Start OCM Event sequence. A flush reset can also be initiated by the OCM_RESET command
(Soft Reset).
All the core logic is reset via a flush reset (except the OCM, Clocks logic, BIST, Flush Reset logic, PLL, DASL
clock generation and macro, and JTAG logic). The scan chains are flushed with ‘0’b, and all other registers
and state machine are forced to their reset values.
The OCM_RESET command only starts the flush reset and does not cause any blocks (other than the one
touched by the flush reset) to be reset.
Bit 15 of the Status register is kept high as long as flush reset is active, and it is cleared when flush reset
completes.
The Flush Reset takes 1 ms to complete.
6.2.3 nTRST Primary Input Reset
The nTRST primary input must be asserted after a system power-on sequence. The nTRST input must be
kept active high during functional operation. During this time, the TMS primary input must be at a high voltage
level (‘1’b).
The nTRST input resets the JTAG logic block and is completely independent of all other reset sequences.
The JTAG logic can only be reset via the nTRST input, and the nTRST input has no effect on any other logic
block.
6.3 Initialization
The PRS28.4G device must be initialized after completion of a Power-On-Reset sequence, a Soft Reset, or a
Built In Self Test (BIST). These three events all cause the Flush Reset sequence to run. After completion of
the Flush Reset, the device is in a standby state. All outputs are tri-stated and data on all inputs is discarded.
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