參數(shù)資料
型號: IBM3288H2848
英文描述: Telecommunication IC
中文描述: 通信集成電路
文件頁數(shù): 60/131頁
文件大?。?/td> 1679K
代理商: IBM3288H2848
PRS28.4G
IBM Packet Routing Switch
Internal Registers
Page 60 of 131
prs28.03.fm
August 31, 2000
10
Control Packet Access Priority Enable
. Guarantees access time to the shared memory by the local proces-
sor for read and write accesses. When set, a shared memory access by the local processor is performed within
a maximum of three LU time units after the command has been issued.
It only has to be set for LU length of 16 or 32 bytes. For other LU lengths, the sequencer operation guarantees
local processor access time to the shared memory independently of the setting of this bit.
11 - 12
Sequencer Sync Pin Mode
. Specifies the operation of the SEQ_SYNC pin.
00:
SEQ_SYNC is tri-stated, and the chip sequencer runs on its own
01:
SEQ_SYNC is an output signal generated by the internal sequencer, which is running on its own
10:
SEQ_SYNC is an input signal on which the internal sequencer synchronizes
11:
Reserved.
13 - 14
Priority Enable
. Controls the cycling process of Output Queue Grant information to the attached adapter.
00:
Priority 0 only enabled
01:
Priority 0 and 1 enabled
10:
Priority 0, 1 and 2 enabled
11:
Priority 0, 1, 2 and 3 enabled
15
Grant Enable
. When is asserted, the insertion of the output queue grant in the outgoing packet header byte is
performed. When deasserted, output queue grant is not inserted, and the received header is transmitted
unchanged.
Bits
Description
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