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| 型號： | IBM3288H2848 |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁數(shù)： | 88/131頁 |
| 文件大小： | 1679K |
| 代理商： | IBM3288H2848 |
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PRS28.4G
IBM Packet Routing Switch
Reset, Initialization, and Operation
Page 88 of 131
prs28.03.fm
August 31, 2000
6. Reset, Initialization, and Operation
6.1 Clock and PLL
PRS28.4G logic contains an internal PLL to generate the high frequency required for the DASL operation.
However, an external PLL can also be used.
6.1.1 Internal PLL
When using the internal PLL, a reference clock must be provided on the SYS_CLK input. The frequency of
reference clock is either a half or a fourth of the byte clock, depending on the setting of the PLL Register.
Also, in order to use the internal PLL, the PLL Register has to be programmed before issuing a Clock Start
OCM Event.
6.1.2 External PLL
When using an external PLL, a clock twice as fast as the internal byte clock has to be provided on the
SYS_CLK input. The C_CLK_OUT byte clock is then used as the reference clock. Note that since the
SYS_CLK clock directly feeds the high speed DASL logic, where both edges of the clock are used to latch
data, the SYS_CLK duty cycle must be 50%.
Notes:
1. Do not access (read or write) the PLL register when an external PLL is used. This guarantees that the
internal PLL stays in reset, and thus in bypass mode, during operation.
2. The external PLL should be locked and generate a stable clock before the Clock Start OCM Event
can be issued.
6.2 Reset
6.2.1 Power-On-Reset Sequence and Clock Start OCM Event
The nRESET primary input must be asserted after a system power-up sequence occurs. It must be active for
at least four EMB bus clock cycles. During this time, the EMB clocks and system clock must be running,
stable, and at the correct frequencies. The EMB_SELECT and EMB_MODE primary inputs must be at a high
voltage level (‘1’b).
The assertion of nRESET causes a discrete reset of the following islands:
OCM and Reset logic
Clocks, BIST, and Flush Reset logic
Internal PLL.
When nRESET is released, the OCM island is functional, while the PLL and Clock/BIST/Flush-Reset logic are
kept in reset state. This is necessary to allow enabling of the internal PLL and its configuration via the PLL
Register. This register should only be accessed when using the internal PLL. The PLL Register physically
resides in the OCM clock domain, and thus does not require the internal core clock to be running in order to
be programmed.
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