參數(shù)資料
型號： IBM3288H2848
英文描述： Telecommunication IC
中文描述： 通信集成電路
文件頁數(shù)： 32/131頁
文件大小： 1679K
代理商： IBM3288H2848
PRS28.4G
IBM Packet Routing Switch
Functional Description
Page 32 of 131
prs28.03.fm
August 31, 2000
Yellow Idle Packets at the egress are considered as Data Packets and therefore do not carry grant priority
bits.
3.2.2 Header Byte H1 and H2
3.2.2.1 Received Packet: Bitmap
Header Bytes H1 and H2 of a received packet carry the destination bit map of the packet. Header Byte H1
carries destination information for output ports 0 through 7, and Header Byte H2 caries destination informa-
tion for output ports 8 through 15.
For Control Packets, the entire bit map field is set to ‘0'. Header Byte H2 is ignored for internal speed expan-
sion.
3.2.2.2 Transmitted Packet: Inband Output Queue Grant Information
Depending on the setting of the Flow Control Enable bit in Configuration Register 0, Header Bytes H1 and H2
provide inband access to the output queue grant information (this access is also provided on device pins).
Using the inband information assumes that it is the same device that transmits and receives packets on the
port.
When flow control is enabled, Header Bytes H1 and H2 carry the output queue grant. The output queue grant
is the grant information given to devices connected to the input ports. This information indicates the status of
the output queues and controls whether or not to transmit packets to the PRS28.4G. This information is
carried for all 16 output ports at the same time for a given priority. Consecutive packets, either idle or data
packet, carry a different priority, cycling from 0 to the highest priority value enabled. For instance, when two
priorities are enabled, it takes two packets to transmit the output queue grant information.
When all four priorities are enabled, the output queue grant information is transmitted in a cycle of four
packets. However, if the Three Threshold Enable bit is set in Configuration Register 0, the cycle is reduced to
3, and grants for priorities 0, 1, and 2 only are sent. It is then assumed that thresholds 2 and 3 are
programmed with the same value.
To synchronize the input interface device fly wheel counter with the inband output queue grant, the priority
value for which the output queue grant is transmitted is carried in the Priority Grant bits of the H0 Packet
Qualifier Byte of Idle Packets. Since inband grant priority is transmitted in cycles of consecutive packets,
priority synchronization is performed on Idle Packets only, and this information is not provided for Data
Packets. However, grant information is always transmitted.
Table 8: Header Byte 1 and 2 and Incoming Packet Bitmap
Bit:
0
1
2
3
4
5
6
7
Header Byte H1
Port:
0
1
2
3
4
5
6
7
Header Byte H2
Port:
8
9
10
11
12
13
14
15
Table 9: Header Byte 0 and 1 and Output queue grant
Bit
0
1
2
3
4
5
6
7
Header Byte H1
Output Queue:
0
1
2
3
4
5
6
7
Header Byte H2
Output Queue:
8
9
10
11
12
13
14
15
相關PDF資料
PDF描述
IBM32NPR100EXXCAB133 Microprocessor
IBM32NPR101EPXCAC133 Microprocessor
IBM37RGB524CF17A Video DAC with Color Palette (RAMDAC)
IBM37RGB524CF22A Video DAC with Color Palette (RAMDAC)
IBM39MPEGS420PBA18C
相關代理商/技術參數(shù)
參數(shù)描述
IBM32NPR100EXXCAB133 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor
IBM32NPR101EPXCAC133 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor
IBM35CPC945C03C-2 制造商:IBM 功能描述:
IBM37RGB524CF17A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC)
IBM37RGB524CF22A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Video DAC with Color Palette (RAMDAC)
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*